Body-bias regulator for ultra low power multifunction CMOS gates

This paper presents a novel technique for biasing multifunction CMOS gates operating in the subthreshold region, to achieve better matching between nMOS and pMOS subthreshold currents. Two different implementations of the minority-3 gate have been simulated in a general purpose 90 nm triple-well pro...

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Bibliographic Details
Main Authors: Granhaug, K., Aunet, S., Lande, T.S.
Format: Conference Proceeding
Language:English
Subjects:
Circuit simulation
CMOS logic circuits
Informatics
Interface states
Logic functions
MOS devices
MOSFET circuits
Regulators
Subthreshold current
Threshold voltage
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Summary:This paper presents a novel technique for biasing multifunction CMOS gates operating in the subthreshold region, to achieve better matching between nMOS and pMOS subthreshold currents. Two different implementations of the minority-3 gate have been simulated in a general purpose 90 nm triple-well process. The proposed regulator circuit increases the degree of symmetry between rise and fall times for both gates, compared to the unregulated case where the wells were tied to a fixed voltage. Simulations also show improved stability across a large temperature range for both circuits when use of the regulator is employed. Through Monte-Carlo simulations for typical process parameters it is also shown that low-level redundancy significantly increases yield for both minority-3 gates
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2006.1692820