The new improved pseudo fractional-N clock generator with 50% duty cycle

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the...

Full description

Saved in:
Bibliographic Details
Main Authors: Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Clocks
CMOS process
CMOS technology
Flowcharts
Frequency
Phase locked loops
System-on-a-chip
Voltage
Voltage-controlled oscillators
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2006.1693547