The new improved pseudo fractional-N clock generator with 50% duty cycle

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the...

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Main Authors: Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Clocks
CMOS process
CMOS technology
Flowcharts
Frequency
Phase locked loops
System-on-a-chip
Voltage
Voltage-controlled oscillators
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creator Shu-Chang Kuo
Tzu-Chien Hung
Wei-Bin Yang
description Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V
doi_str_mv 10.1109/ISCAS.2006.1693547
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1693547</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1693547</ieee_id><sourcerecordid>1693547</sourcerecordid><originalsourceid>FETCH-ieee_primary_16935473</originalsourceid><addsrcrecordid>eNp9jrFuwjAURZ9KKxEoP1CWtzAmPNsxiccKtaILC-zIch7FbYgjJxTl78vAzF2Ojs5yAd4EZUKQWX7t1u-7TBKtMrEySufFEyRS6DIVWuoRTKgoSRlVGvMMCclCpLkiOYZZ1_3Qbbm-OSWw2Z8YG76iP7cx_HGFbceXKuAxWtf70Ng63aKrg_vFb2442j5EvPr-hJoWWF36Ad3gan6Fl6OtO57dOYX558d-vUk9Mx_a6M82Dof7WfW4_gP5Wz78</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>The new improved pseudo fractional-N clock generator with 50% duty cycle</title><source>IEEE Xplore All Conference Series</source><creator>Shu-Chang Kuo ; Tzu-Chien Hung ; Wei-Bin Yang</creator><creatorcontrib>Shu-Chang Kuo ; Tzu-Chien Hung ; Wei-Bin Yang</creatorcontrib><description>Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 0780393899</identifier><identifier>ISBN: 9780780393899</identifier><identifier>EISSN: 2158-1525</identifier><identifier>DOI: 10.1109/ISCAS.2006.1693547</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; Clocks ; CMOS process ; CMOS technology ; Flowcharts ; Frequency ; Phase locked loops ; System-on-a-chip ; Voltage ; Voltage-controlled oscillators</subject><ispartof>2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1693547$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1693547$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Shu-Chang Kuo</creatorcontrib><creatorcontrib>Tzu-Chien Hung</creatorcontrib><creatorcontrib>Wei-Bin Yang</creatorcontrib><title>The new improved pseudo fractional-N clock generator with 50% duty cycle</title><title>2006 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V</description><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Flowcharts</subject><subject>Frequency</subject><subject>Phase locked loops</subject><subject>System-on-a-chip</subject><subject>Voltage</subject><subject>Voltage-controlled oscillators</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>0780393899</isbn><isbn>9780780393899</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9jrFuwjAURZ9KKxEoP1CWtzAmPNsxiccKtaILC-zIch7FbYgjJxTl78vAzF2Ojs5yAd4EZUKQWX7t1u-7TBKtMrEySufFEyRS6DIVWuoRTKgoSRlVGvMMCclCpLkiOYZZ1_3Qbbm-OSWw2Z8YG76iP7cx_HGFbceXKuAxWtf70Ng63aKrg_vFb2442j5EvPr-hJoWWF36Ad3gan6Fl6OtO57dOYX558d-vUk9Mx_a6M82Dof7WfW4_gP5Wz78</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Shu-Chang Kuo</creator><creator>Tzu-Chien Hung</creator><creator>Wei-Bin Yang</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>The new improved pseudo fractional-N clock generator with 50% duty cycle</title><author>Shu-Chang Kuo ; Tzu-Chien Hung ; Wei-Bin Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_16935473</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Circuits</topic><topic>Clocks</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Flowcharts</topic><topic>Frequency</topic><topic>Phase locked loops</topic><topic>System-on-a-chip</topic><topic>Voltage</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Shu-Chang Kuo</creatorcontrib><creatorcontrib>Tzu-Chien Hung</creatorcontrib><creatorcontrib>Wei-Bin Yang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shu-Chang Kuo</au><au>Tzu-Chien Hung</au><au>Wei-Bin Yang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The new improved pseudo fractional-N clock generator with 50% duty cycle</atitle><btitle>2006 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2006</date><risdate>2006</risdate><spage>4 pp.</spage><pages>4 pp.-</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>0780393899</isbn><isbn>9780780393899</isbn><abstract>Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2006.1693547</doi></addata></record>
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source IEEE Xplore All Conference Series
subjects Circuits
Clocks
CMOS process
CMOS technology
Flowcharts
Frequency
Phase locked loops
System-on-a-chip
Voltage
Voltage-controlled oscillators
title The new improved pseudo fractional-N clock generator with 50% duty cycle
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T23%3A22%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=The%20new%20improved%20pseudo%20fractional-N%20clock%20generator%20with%2050%25%20duty%20cycle&rft.btitle=2006%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Shu-Chang%20Kuo&rft.date=2006&rft.spage=4%20pp.&rft.pages=4%20pp.-&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=0780393899&rft.isbn_list=9780780393899&rft_id=info:doi/10.1109/ISCAS.2006.1693547&rft_dat=%3Cieee_CHZPO%3E1693547%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-ieee_primary_16935473%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1693547&rfr_iscdi=true