Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC

Context-based adaptive variable-length coding (CAVLC) is a new and important feature of the latest video coding standard, H.264/AVC. The direct VLSI implementation of CAVLC modified from the conventional run-length coding architecture will lead to low throughput and utilization. In this brief, an ef...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2006-09, Vol.53 (9), p.832-836
Main Authors: Chen, T.-C., Huang, Y.-W., Tsai, C.-Y., Hsieh, B.-Y., Chen, L.-G.
Format: Article
Language:English
Subjects:
Architecture
Automatic voltage control
Bit rate
Coding
Coding standards
Context-based adaptive variable-length coding (CAVLC)
Design engineering
Encapsulation
Engine blocks
Engines
Entropy
H.264/AVC
Parallel processing
Pipeline processing
Symbols
Throughput
Utilization
Very large scale integration
Video coding
VLSI architecture
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Summary:Context-based adaptive variable-length coding (CAVLC) is a new and important feature of the latest video coding standard, H.264/AVC. The direct VLSI implementation of CAVLC modified from the conventional run-length coding architecture will lead to low throughput and utilization. In this brief, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4 times 4 blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bitstream. Our dual-block-pipelined architecture doubles the throughput and utilization of CAVLC at high bit rates. Moreover, a zero skipping technique is adopted to reduce up to 90% of cycles at low bit rates. Last but not least, Exp-Golomb coding for other general symbols and bitstream encapsulation for the network abstraction layer are integrated with CAVLC as a complete H.264/AVC baseline profile entropy coder. Simulation shows that our design is capable of real-time processing for 1920 times 1088 30-fps videos with 23.6 K logic gates at 100 MHz
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2006.880014