Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology

The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower suppl...

Full description

Saved in:
Bibliographic Details
Main Authors: Ozawa, O., Fukuoka, K., Igarashi, Y., Kuraishi, T., Yasu, Y., Maki, Y., Ipposhi, T., Ochiai, T., Shirahata, M., Ishibashi, K.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
CMOS logic circuits
CMOS technology
Delay
Inverters
Isolation technology
Logic circuits
Logic devices
Logic gates
Low voltage
Voltage control
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 187
container_issue
container_start_page 186
container_title
container_volume
creator Ozawa, O.
Fukuoka, K.
Igarashi, Y.
Kuraishi, T.
Yasu, Y.
Maki, Y.
Ipposhi, T.
Ochiai, T.
Shirahata, M.
Ishibashi, K.
description The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively
doi_str_mv 10.1109/VLSIC.2006.1705372
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1705372</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1705372</ieee_id><sourcerecordid>1705372</sourcerecordid><originalsourceid>FETCH-LOGICAL-i156t-c6e61f39f451ac7c20579fbb79b3301f2a1a8cb955044eabfff46d62724b22363</originalsourceid><addsrcrecordid>eNotkE1Lw0AYhBdUsNT-Ab3sUQ9b33c_m2ONX4FAA029lt24266kWUkqxX9vwJ6GGYaHYQi5RZgjQvb4Ua6LfM4B9BwNKGH4BZllZoGSSwljrC7JhKNaMKUBr8lsGL7GGESmlOITsi_TiVbp5Hu6XuX02Q9x19HNELsdrWx_jLZlde-7Zs-KIbX2GFNHl0_52C7ofVUX7GweaEgj48cxBGDdgZbruqK1b_ZdatPu94ZcBdsOfnbWKdm8vtT5OytXb0W-LFlEpY-s0V5jEFmQCm1jGg7KZME5kzkhAAO3aBeNG9eDlN66EILUn5obLh3nQospufvnRu_99ruPB9v_bs_fiD9CTVQz</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology</title><source>IEEE Xplore All Conference Series</source><creator>Ozawa, O. ; Fukuoka, K. ; Igarashi, Y. ; Kuraishi, T. ; Yasu, Y. ; Maki, Y. ; Ipposhi, T. ; Ochiai, T. ; Shirahata, M. ; Ishibashi, K.</creator><creatorcontrib>Ozawa, O. ; Fukuoka, K. ; Igarashi, Y. ; Kuraishi, T. ; Yasu, Y. ; Maki, Y. ; Ipposhi, T. ; Ochiai, T. ; Shirahata, M. ; Ishibashi, K.</creatorcontrib><description>The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively</description><identifier>ISSN: 2158-5601</identifier><identifier>ISBN: 9781424400065</identifier><identifier>ISBN: 1424400066</identifier><identifier>DOI: 10.1109/VLSIC.2006.1705372</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>CMOS logic circuits ; CMOS technology ; Delay ; Inverters ; Isolation technology ; Logic circuits ; Logic devices ; Logic gates ; Low voltage ; Voltage control</subject><ispartof>2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, p.186-187</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1705372$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1705372$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ozawa, O.</creatorcontrib><creatorcontrib>Fukuoka, K.</creatorcontrib><creatorcontrib>Igarashi, Y.</creatorcontrib><creatorcontrib>Kuraishi, T.</creatorcontrib><creatorcontrib>Yasu, Y.</creatorcontrib><creatorcontrib>Maki, Y.</creatorcontrib><creatorcontrib>Ipposhi, T.</creatorcontrib><creatorcontrib>Ochiai, T.</creatorcontrib><creatorcontrib>Shirahata, M.</creatorcontrib><creatorcontrib>Ishibashi, K.</creatorcontrib><title>Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology</title><title>2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers</title><addtitle>VLSIC</addtitle><description>The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively</description><subject>CMOS logic circuits</subject><subject>CMOS technology</subject><subject>Delay</subject><subject>Inverters</subject><subject>Isolation technology</subject><subject>Logic circuits</subject><subject>Logic devices</subject><subject>Logic gates</subject><subject>Low voltage</subject><subject>Voltage control</subject><issn>2158-5601</issn><isbn>9781424400065</isbn><isbn>1424400066</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkE1Lw0AYhBdUsNT-Ab3sUQ9b33c_m2ONX4FAA029lt24266kWUkqxX9vwJ6GGYaHYQi5RZgjQvb4Ua6LfM4B9BwNKGH4BZllZoGSSwljrC7JhKNaMKUBr8lsGL7GGESmlOITsi_TiVbp5Hu6XuX02Q9x19HNELsdrWx_jLZlde-7Zs-KIbX2GFNHl0_52C7ofVUX7GweaEgj48cxBGDdgZbruqK1b_ZdatPu94ZcBdsOfnbWKdm8vtT5OytXb0W-LFlEpY-s0V5jEFmQCm1jGg7KZME5kzkhAAO3aBeNG9eDlN66EILUn5obLh3nQospufvnRu_99ruPB9v_bs_fiD9CTVQz</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Ozawa, O.</creator><creator>Fukuoka, K.</creator><creator>Igarashi, Y.</creator><creator>Kuraishi, T.</creator><creator>Yasu, Y.</creator><creator>Maki, Y.</creator><creator>Ipposhi, T.</creator><creator>Ochiai, T.</creator><creator>Shirahata, M.</creator><creator>Ishibashi, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology</title><author>Ozawa, O. ; Fukuoka, K. ; Igarashi, Y. ; Kuraishi, T. ; Yasu, Y. ; Maki, Y. ; Ipposhi, T. ; Ochiai, T. ; Shirahata, M. ; Ishibashi, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i156t-c6e61f39f451ac7c20579fbb79b3301f2a1a8cb955044eabfff46d62724b22363</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2006</creationdate><topic>CMOS logic circuits</topic><topic>CMOS technology</topic><topic>Delay</topic><topic>Inverters</topic><topic>Isolation technology</topic><topic>Logic circuits</topic><topic>Logic devices</topic><topic>Logic gates</topic><topic>Low voltage</topic><topic>Voltage control</topic><toplevel>online_resources</toplevel><creatorcontrib>Ozawa, O.</creatorcontrib><creatorcontrib>Fukuoka, K.</creatorcontrib><creatorcontrib>Igarashi, Y.</creatorcontrib><creatorcontrib>Kuraishi, T.</creatorcontrib><creatorcontrib>Yasu, Y.</creatorcontrib><creatorcontrib>Maki, Y.</creatorcontrib><creatorcontrib>Ipposhi, T.</creatorcontrib><creatorcontrib>Ochiai, T.</creatorcontrib><creatorcontrib>Shirahata, M.</creatorcontrib><creatorcontrib>Ishibashi, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ozawa, O.</au><au>Fukuoka, K.</au><au>Igarashi, Y.</au><au>Kuraishi, T.</au><au>Yasu, Y.</au><au>Maki, Y.</au><au>Ipposhi, T.</au><au>Ochiai, T.</au><au>Shirahata, M.</au><au>Ishibashi, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology</atitle><btitle>2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers</btitle><stitle>VLSIC</stitle><date>2006</date><risdate>2006</risdate><spage>186</spage><epage>187</epage><pages>186-187</pages><issn>2158-5601</issn><isbn>9781424400065</isbn><isbn>1424400066</isbn><abstract>The bodies of partially depleted SOI devices are selectively biased so that circuits operate at low supply voltages without area overhead. Applying forward body bias to logic gates reduces delay variation by 7-21%. A level shifter (LF) and data retention FF (DRFF) circuits can operate at lower supply voltages below 1.0-V when the body bias of the key transistors is suitably controlled. The technology reduces operating and standby power of SOC with 90-nm LSTP CMOS technology by 40 and 98%, respectively</abstract><pub>IEEE</pub><doi>10.1109/VLSIC.2006.1705372</doi><tpages>2</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 2158-5601
ispartof 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, p.186-187
issn 2158-5601
language eng ; jpn
recordid cdi_ieee_primary_1705372
source IEEE Xplore All Conference Series
subjects CMOS logic circuits
CMOS technology
Delay
Inverters
Isolation technology
Logic circuits
Logic devices
Logic gates
Low voltage
Voltage control
title Low Power SOC Design Using Partial-Trench-Isolation ABC SOI (PTI-ABC SOI) for Sub-100-nm LSTP Technology
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T17%3A58%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Low%20Power%20SOC%20Design%20Using%20Partial-Trench-Isolation%20ABC%20SOI%20(PTI-ABC%20SOI)%20for%20Sub-100-nm%20LSTP%20Technology&rft.btitle=2006%20Symposium%20on%20VLSI%20Circuits,%202006.%20Digest%20of%20Technical%20Papers&rft.au=Ozawa,%20O.&rft.date=2006&rft.spage=186&rft.epage=187&rft.pages=186-187&rft.issn=2158-5601&rft.isbn=9781424400065&rft.isbn_list=1424400066&rft_id=info:doi/10.1109/VLSIC.2006.1705372&rft_dat=%3Cieee_CHZPO%3E1705372%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i156t-c6e61f39f451ac7c20579fbb79b3301f2a1a8cb955044eabfff46d62724b22363%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1705372&rfr_iscdi=true