Loading…
A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering
We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the parameters (e.g., orientation, bandwidth) of the Gabor-type filter and can be modified at runtime so that the functionality of...
Saved in:
Main Authors: | , , , |
---|---|
Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 20 |
container_issue | |
container_start_page | 15 |
container_title | |
container_volume | |
creator | Cheung, O.Y.H. Leong, P.H.W. Tsang, E.K.C. Shi, B.E. |
description | We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the parameters (e.g., orientation, bandwidth) of the Gabor-type filter and can be modified at runtime so that the functionality of Gabor-type filter can be changed dynamically. Our implementation uses the Euler method to solve the ordinary differential equation describing the CNN. The design is scalable to allow for different pixel array sizes, as well as simultaneous computation of multiple filter outputs tuned to different orientations and bandwidths. For 1024 pixel frames, an implementation on a Xilinx Virtex XC2V1000-4 device uses 1842 slices, operates at 120 MHz and achieves 23,000 Euler iterations over one frame per second. |
doi_str_mv | 10.1109/IJCNN.2006.246653 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_1716064</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1716064</ieee_id><sourcerecordid>1716064</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-f0d901ce9d08bff54de20c7a2f9bc58ff1d492594cb15ed4898a96740a4f542d3</originalsourceid><addsrcrecordid>eNo1jNtKw0AURQcvYK39APFlfiD1zCWTnMcQbK2UKlSfyyQ5I9HJhUmK9O8bUGHDethrb8buBSyFAHzcvOS73VICmKXUxsTqgs2kMCLSGpJLtsAkhSkKNYK8-u8Uqht2OwxfAFIhqhnbZ3xfWm8LT3z1ts74puk9NdSOdqy7lneO5-T90dvAd3QM1k8Yf7rwPXDXBb62RRei8dRP89qPFOr2845dO-sHWvxxzj5WT-_5c7R9XW_ybBvVIonHyEGFIErCCtLCuVhXJKFMrHRYlHHqnKg0yhh1WYiYKp1iatEkGqyeZFmpOXv4_a2J6NCHurHhdBCJMGC0OgM-vFHx</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering</title><source>IEEE Xplore All Conference Series</source><creator>Cheung, O.Y.H. ; Leong, P.H.W. ; Tsang, E.K.C. ; Shi, B.E.</creator><creatorcontrib>Cheung, O.Y.H. ; Leong, P.H.W. ; Tsang, E.K.C. ; Shi, B.E.</creatorcontrib><description>We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the parameters (e.g., orientation, bandwidth) of the Gabor-type filter and can be modified at runtime so that the functionality of Gabor-type filter can be changed dynamically. Our implementation uses the Euler method to solve the ordinary differential equation describing the CNN. The design is scalable to allow for different pixel array sizes, as well as simultaneous computation of multiple filter outputs tuned to different orientations and bandwidths. For 1024 pixel frames, an implementation on a Xilinx Virtex XC2V1000-4 device uses 1842 slices, operates at 120 MHz and achieves 23,000 Euler iterations over one frame per second.</description><identifier>ISSN: 2161-4393</identifier><identifier>ISBN: 9780780394902</identifier><identifier>ISBN: 0780394909</identifier><identifier>EISSN: 2161-4407</identifier><identifier>DOI: 10.1109/IJCNN.2006.246653</identifier><language>eng</language><publisher>IEEE</publisher><subject>Biological system modeling ; Biology computing ; Biomedical signal processing ; Cellular neural networks ; Energy consumption ; Field programmable gate arrays ; Gabor filters ; Retina ; Very large scale integration ; Visual system</subject><ispartof>The 2006 IEEE International Joint Conference on Neural Network Proceedings, 2006, p.15-20</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1716064$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2057,4049,4050,27924,54554,54919,54931</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1716064$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Cheung, O.Y.H.</creatorcontrib><creatorcontrib>Leong, P.H.W.</creatorcontrib><creatorcontrib>Tsang, E.K.C.</creatorcontrib><creatorcontrib>Shi, B.E.</creatorcontrib><title>A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering</title><title>The 2006 IEEE International Joint Conference on Neural Network Proceedings</title><addtitle>IJCNN</addtitle><description>We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the parameters (e.g., orientation, bandwidth) of the Gabor-type filter and can be modified at runtime so that the functionality of Gabor-type filter can be changed dynamically. Our implementation uses the Euler method to solve the ordinary differential equation describing the CNN. The design is scalable to allow for different pixel array sizes, as well as simultaneous computation of multiple filter outputs tuned to different orientations and bandwidths. For 1024 pixel frames, an implementation on a Xilinx Virtex XC2V1000-4 device uses 1842 slices, operates at 120 MHz and achieves 23,000 Euler iterations over one frame per second.</description><subject>Biological system modeling</subject><subject>Biology computing</subject><subject>Biomedical signal processing</subject><subject>Cellular neural networks</subject><subject>Energy consumption</subject><subject>Field programmable gate arrays</subject><subject>Gabor filters</subject><subject>Retina</subject><subject>Very large scale integration</subject><subject>Visual system</subject><issn>2161-4393</issn><issn>2161-4407</issn><isbn>9780780394902</isbn><isbn>0780394909</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1jNtKw0AURQcvYK39APFlfiD1zCWTnMcQbK2UKlSfyyQ5I9HJhUmK9O8bUGHDethrb8buBSyFAHzcvOS73VICmKXUxsTqgs2kMCLSGpJLtsAkhSkKNYK8-u8Uqht2OwxfAFIhqhnbZ3xfWm8LT3z1ts74puk9NdSOdqy7lneO5-T90dvAd3QM1k8Yf7rwPXDXBb62RRei8dRP89qPFOr2845dO-sHWvxxzj5WT-_5c7R9XW_ybBvVIonHyEGFIErCCtLCuVhXJKFMrHRYlHHqnKg0yhh1WYiYKp1iatEkGqyeZFmpOXv4_a2J6NCHurHhdBCJMGC0OgM-vFHx</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Cheung, O.Y.H.</creator><creator>Leong, P.H.W.</creator><creator>Tsang, E.K.C.</creator><creator>Shi, B.E.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering</title><author>Cheung, O.Y.H. ; Leong, P.H.W. ; Tsang, E.K.C. ; Shi, B.E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f0d901ce9d08bff54de20c7a2f9bc58ff1d492594cb15ed4898a96740a4f542d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Biological system modeling</topic><topic>Biology computing</topic><topic>Biomedical signal processing</topic><topic>Cellular neural networks</topic><topic>Energy consumption</topic><topic>Field programmable gate arrays</topic><topic>Gabor filters</topic><topic>Retina</topic><topic>Very large scale integration</topic><topic>Visual system</topic><toplevel>online_resources</toplevel><creatorcontrib>Cheung, O.Y.H.</creatorcontrib><creatorcontrib>Leong, P.H.W.</creatorcontrib><creatorcontrib>Tsang, E.K.C.</creatorcontrib><creatorcontrib>Shi, B.E.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cheung, O.Y.H.</au><au>Leong, P.H.W.</au><au>Tsang, E.K.C.</au><au>Shi, B.E.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering</atitle><btitle>The 2006 IEEE International Joint Conference on Neural Network Proceedings</btitle><stitle>IJCNN</stitle><date>2006</date><risdate>2006</risdate><spage>15</spage><epage>20</epage><pages>15-20</pages><issn>2161-4393</issn><eissn>2161-4407</eissn><isbn>9780780394902</isbn><isbn>0780394909</isbn><abstract>We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the parameters (e.g., orientation, bandwidth) of the Gabor-type filter and can be modified at runtime so that the functionality of Gabor-type filter can be changed dynamically. Our implementation uses the Euler method to solve the ordinary differential equation describing the CNN. The design is scalable to allow for different pixel array sizes, as well as simultaneous computation of multiple filter outputs tuned to different orientations and bandwidths. For 1024 pixel frames, an implementation on a Xilinx Virtex XC2V1000-4 device uses 1842 slices, operates at 120 MHz and achieves 23,000 Euler iterations over one frame per second.</abstract><pub>IEEE</pub><doi>10.1109/IJCNN.2006.246653</doi><tpages>6</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 2161-4393 |
ispartof | The 2006 IEEE International Joint Conference on Neural Network Proceedings, 2006, p.15-20 |
issn | 2161-4393 2161-4407 |
language | eng |
recordid | cdi_ieee_primary_1716064 |
source | IEEE Xplore All Conference Series |
subjects | Biological system modeling Biology computing Biomedical signal processing Cellular neural networks Energy consumption Field programmable gate arrays Gabor filters Retina Very large scale integration Visual system |
title | A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T18%3A46%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Scalable%20FPGA%20Implementation%20of%20Cellular%20Neural%20Networks%20for%20Gabor-type%20Filtering&rft.btitle=The%202006%20IEEE%20International%20Joint%20Conference%20on%20Neural%20Network%20Proceedings&rft.au=Cheung,%20O.Y.H.&rft.date=2006&rft.spage=15&rft.epage=20&rft.pages=15-20&rft.issn=2161-4393&rft.eissn=2161-4407&rft.isbn=9780780394902&rft.isbn_list=0780394909&rft_id=info:doi/10.1109/IJCNN.2006.246653&rft_dat=%3Cieee_CHZPO%3E1716064%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-f0d901ce9d08bff54de20c7a2f9bc58ff1d492594cb15ed4898a96740a4f542d3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1716064&rfr_iscdi=true |