Hierarchical parameterized synthesis of semi regular VLSI processor arrays

The authors describe a system for the synthesis of semi-regular processor arrays. They discuss the generation of control and memory for the initialization of the feedback loops of the processors in a processor array, and for the rerouting of I/O data from the array boundaries to specific I/O process...

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Bibliographic Details
Main Authors: de Lange, A.A.J., Deprettere, E.F., Dewilde, P.M.
Format: Conference Proceeding
Language:English
Subjects:
Communication system control
Computer architecture
Control system synthesis
Feedback loop
Logic arrays
Parallel processing
Signal processing
Size control
Throughput
Very large scale integration
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Summary:The authors describe a system for the synthesis of semi-regular processor arrays. They discuss the generation of control and memory for the initialization of the feedback loops of the processors in a processor array, and for the rerouting of I/O data from the array boundaries to specific I/O processors in the array. Moreover, they deal with the mapping of a parameterized or full-size processor array to a reduced-size processor array architecture as well as the generation of the necessary control and memory that is involved in this.< >
DOI:10.1109/ISCAS.1991.176319