Design for testability and built-in self test: a review

A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point i...

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Bibliographic Details
Published in:IEEE transactions on industrial electronics (1982) 1989-05, Vol.36 (2), p.129-140
Main Authors: Nagle, H.T., Roy, S.C., Hawkins, C.F., McNamer, M.G., Fritzemeier, R.R.
Format: Article
Language:English
Subjects:
Automatic testing
Built-in self-test
Circuit testing
Controllability
Data compression
Design for testability
Hardware
Logic testing
Observability
Very large scale integration
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Summary:A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered.< >
ISSN:0278-0046
1557-9948
DOI:10.1109/41.19062