A 1000 MIPS BiCMOS microprocessor with superscalar architecture

A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, fi...

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Bibliographic Details
Main Authors: Nishii, O., Hanawa, M., Nishimukai, T., Suzuki, M., Yano, K., Hiraki, M., Shukuri, S., Nishida, T.
Format: Conference Proceeding
Language:English
Subjects:
Adders
BiCMOS integrated circuits
Clocks
Decoding
Delay
Logic
Microprocessors
Pipelines
Registers
Sliding mode control
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Summary:A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, file, and ALU (arithmetic and logic unit) operating at 250 MHz.< >
DOI:10.1109/ISSCC.1992.200438