Delay test generation. II. Algebra and algorithms

For pt.I see ibid., p.857-66 (1988). A novel algebra is introduced for delay test generation. The algebra combines the nine natural logic values (00 , 01, 0X, 10, 11, 1X, X1, XX) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebrai...

Full description

Saved in:
Bibliographic Details
Main Authors: Iyengar, V.S., Rosen, B.K., Spillinger, I.
Format: Conference Proceeding
Language:English
Subjects:
Algebra
Circuit faults
Circuit testing
Clocks
Delay effects
Discrete event simulation
Latches
Logic testing
Propagation delay
Robustness
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:For pt.I see ibid., p.857-66 (1988). A novel algebra is introduced for delay test generation. The algebra combines the nine natural logic values (00 , 01, 0X, 10, 11, 1X, X1, XX) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e. without numerical computations using actual gate delays). A test generator uses this algebra in an efficiently organized backtrack search. The test generator is linked to a delay fault simulator. Previous event-driven simulators have considered different types of events; one type of event is a change in faultless values from one test to another test, and the other type of event is a difference between faulty and faultless values. The presented simulator is driven by both types of events. Each generated test is simulated to determine the quality of detection.< >
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.1988.207874