Comparison of aliasing probability for multiple MISRs and M-stage MISRs with m inputs

MISRs are widely used as signature circuits for VLSI built-in self-tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is greater than m. The aliasing probability as a function of the test length for these signature circuits is a...

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Bibliographic Details
Main Authors: Iwasaki, K., Shou-Ping Feng, Fujiwara, T., Kasami, T.
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
Equations
Linear code
Parity check codes
Polynomials
Probability
Reed-Solomon codes
Registers
Sequential circuits
Vectors
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Summary:MISRs are widely used as signature circuits for VLSI built-in self-tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is greater than m. The aliasing probability as a function of the test length for these signature circuits is analyzed for a binary symmetric channel. It is shown that the peak aliasing probability of the double MISRs is less than that of an M-stage MISR with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2/sup -dm/ and that for an M-stage MISR with m inputs is 2/sup -M/ if it is characterized by a primitive polynomial. The double MISR is recommended to reduce the aliasing probability of signature circuits.< >
DOI:10.1109/RFTS.1991.212962