Deterministic model and transient analysis of virtual circuits

• Published in: IEEE transactions on software engineering 1993-02, Vol.19 (2), p.187-197
• Main Authors: Agrawala, A.K., Jain, B.N.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit analysis; Circuits; Computer engineering; Computer networks; Computer science; Computer science; control theory; systems; Delay; Exact sciences and technology; Information processing; Information systems; Networks and services in france and abroad; Processor scheduling; Random variables; Relays; Routing; Servers; Simulation; Software; Software engineering; Systems development; Telecommunications; Telecommunications and information theory; Teleprocessing networks. Isdn; Throughput; Time factors; Traffic congestion; Transient analysis
• ISSN: 0098-5589; 1939-3520
• DOI: 10.1109/32.214835

A model for a virtual circuit in the form of a tandem of servers that process incoming packets using a FIFO (first-in, first-out) discipline is proposed. The service times are assumed to be known completely. These may differ from packet to packet and from server to server. The model permits a variety of buffer or transit time constraints to be incorporated into the model. Several results that help one to understand the transient behavior of a virtual circuit are presented. On the basis of these results, a number of schemes that may be used to determine the time when the next packet must be sent over the network are presented. Transit delay and throughput are used to evaluate a given schedule. Solutions are given for maximum throughput, minimum transit delay, and maximum throughput under transit delay constraints. It is expected that these results will have a substantial bearing on the study of congestion control policies in computer networks, particularly those based on predicting network behavior.< >