An encoder/decoder chip set for the MPEG video standard

A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms a...

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Bibliographic Details
Main Authors: Tamitani, I., Ohta, M., Ooi, Y., Yoshida, A., Nomura, M., Koyama, H., Nishitani, T.
Format: Conference Proceeding
Language:English
Subjects:
Costs
Data communication
Decoding
Digital signal processing chips
Encoding
MPEG standards
Partitioning algorithms
Quantization
Transform coding
Very large scale integration
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Summary:A VLSI chip set capable of real-time MPEG (Moving Picture Experts Group) video encoding/decoding has been developed. It is composed of an inter-frame prediction chip, a transform and quantization chip, and a variable length coding chip. To make the chip set more cost effective, the MPEG algorithms are first partitioned into three blocks on the basis of their characteristics. Individual chip architectures are designed with the use of programmable DSP and application specific array approaches. A hierarchical data transmission method is introduced for use among the chips and frame memories. By using three chips, an MPEG video encounter can compress a 30-frames/s image sequence of 352 pels*240 lines. A decoder can be constructed with two chips for the same sequence.< >
ISSN:1520-6149
2379-190X
DOI:10.1109/ICASSP.1992.226509