A new on-chip voltage regulator for high density CMOS DRAMs

The authors report on new voltage regulator circuitry used in a 4 Mb CMOS DRAM. The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees...

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Bibliographic Details
Main Authors: Mao, R.S., Chao, H.H., Chi, Y.C., Chung, P.W., Hsieh, C.H., Lin, C.M., Lu, N.C.C., Lan, S.Y., Liu, Y.F., Lin, M.Z., Wang, D.W., Tuan, H.C., Tsai, H.H., Lu, C.Y.
Format: Conference Proceeding
Language:English
Subjects:
Chaos
Delay
Energy consumption
MOSFET circuits
Power supplies
Random access memory
Regulators
Temperature
Voltage
Voltage-controlled oscillators
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Summary:The authors report on new voltage regulator circuitry used in a 4 Mb CMOS DRAM. The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees C), while V/sub DD/ varies from 3.3 to 6.2 V. V/sub INT/ presents a positive temperature coefficient, which is adjustable, to compensate the higher cell leakage and the slowdown of MOSFET operations at higher temperature. While V/sub DD/ is raised above 6.3 V, the regulator enters the burn-in mode where V/sub INT/ follows a 2/3 V/sub DD/ curve, which gives an exact internal burn-in voltage as desired. This internal burn-in voltage is insensitive to temperature and process variations.< >
DOI:10.1109/VLSIC.1992.229268