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A new on-chip voltage regulator for high density CMOS DRAMs
The authors report on new voltage regulator circuitry used in a 4 Mb CMOS DRAM. The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees...
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| creator | Mao, R.S. Chao, H.H. Chi, Y.C. Chung, P.W. Hsieh, C.H. Lin, C.M. Lu, N.C.C. Lan, S.Y. Liu, Y.F. Lin, M.Z. Wang, D.W. Tuan, H.C. Tsai, H.H. Lu, C.Y. |
| description | The authors report on new voltage regulator circuitry used in a 4 Mb CMOS DRAM. The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees C), while V/sub DD/ varies from 3.3 to 6.2 V. V/sub INT/ presents a positive temperature coefficient, which is adjustable, to compensate the higher cell leakage and the slowdown of MOSFET operations at higher temperature. While V/sub DD/ is raised above 6.3 V, the regulator enters the burn-in mode where V/sub INT/ follows a 2/3 V/sub DD/ curve, which gives an exact internal burn-in voltage as desired. This internal burn-in voltage is insensitive to temperature and process variations.< > |
| doi_str_mv | 10.1109/VLSIC.1992.229268 |
| format | conference_proceeding |
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The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees C), while V/sub DD/ varies from 3.3 to 6.2 V. V/sub INT/ presents a positive temperature coefficient, which is adjustable, to compensate the higher cell leakage and the slowdown of MOSFET operations at higher temperature. While V/sub DD/ is raised above 6.3 V, the regulator enters the burn-in mode where V/sub INT/ follows a 2/3 V/sub DD/ curve, which gives an exact internal burn-in voltage as desired. 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The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees C), while V/sub DD/ varies from 3.3 to 6.2 V. V/sub INT/ presents a positive temperature coefficient, which is adjustable, to compensate the higher cell leakage and the slowdown of MOSFET operations at higher temperature. While V/sub DD/ is raised above 6.3 V, the regulator enters the burn-in mode where V/sub INT/ follows a 2/3 V/sub DD/ curve, which gives an exact internal burn-in voltage as desired. This internal burn-in voltage is insensitive to temperature and process variations.< ></description><subject>Chaos</subject><subject>Delay</subject><subject>Energy consumption</subject><subject>MOSFET circuits</subject><subject>Power supplies</subject><subject>Random access memory</subject><subject>Regulators</subject><subject>Temperature</subject><subject>Voltage</subject><subject>Voltage-controlled oscillators</subject><isbn>0780307011</isbn><isbn>9780780307018</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1992</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpjYJA0NNAzNDSw1A_zCfZ01jO0tDTSMzKyNDKzYGbgMjC3MDA2MDcwNORg4C0uzjIAAgsjcwsTE04Ga0eFvNRyhfw83eSMzAKFsvycksT0VIWi1PTSnMSS_CKFNCDOyEzPUEhJzSvOLKlUcPb1D1ZwCXL0LeZhYE1LzClO5YXS3AxSbq4hzh66mampqfEFRZm5iUWV8RBnGOOVBACr6TVZ</recordid><startdate>1992</startdate><enddate>1992</enddate><creator>Mao, R.S.</creator><creator>Chao, H.H.</creator><creator>Chi, Y.C.</creator><creator>Chung, P.W.</creator><creator>Hsieh, C.H.</creator><creator>Lin, C.M.</creator><creator>Lu, N.C.C.</creator><creator>Lan, S.Y.</creator><creator>Liu, Y.F.</creator><creator>Lin, M.Z.</creator><creator>Wang, D.W.</creator><creator>Tuan, H.C.</creator><creator>Tsai, H.H.</creator><creator>Lu, C.Y.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1992</creationdate><title>A new on-chip voltage regulator for high density CMOS DRAMs</title><author>Mao, R.S. ; Chao, H.H. ; Chi, Y.C. ; Chung, P.W. ; Hsieh, C.H. ; Lin, C.M. ; Lu, N.C.C. ; Lan, S.Y. ; Liu, Y.F. ; Lin, M.Z. ; Wang, D.W. ; Tuan, H.C. ; Tsai, H.H. ; Lu, C.Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_2292683</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1992</creationdate><topic>Chaos</topic><topic>Delay</topic><topic>Energy consumption</topic><topic>MOSFET circuits</topic><topic>Power supplies</topic><topic>Random access memory</topic><topic>Regulators</topic><topic>Temperature</topic><topic>Voltage</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Mao, R.S.</creatorcontrib><creatorcontrib>Chao, H.H.</creatorcontrib><creatorcontrib>Chi, Y.C.</creatorcontrib><creatorcontrib>Chung, P.W.</creatorcontrib><creatorcontrib>Hsieh, C.H.</creatorcontrib><creatorcontrib>Lin, C.M.</creatorcontrib><creatorcontrib>Lu, N.C.C.</creatorcontrib><creatorcontrib>Lan, S.Y.</creatorcontrib><creatorcontrib>Liu, Y.F.</creatorcontrib><creatorcontrib>Lin, M.Z.</creatorcontrib><creatorcontrib>Wang, D.W.</creatorcontrib><creatorcontrib>Tuan, H.C.</creatorcontrib><creatorcontrib>Tsai, H.H.</creatorcontrib><creatorcontrib>Lu, C.Y.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Explore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mao, R.S.</au><au>Chao, H.H.</au><au>Chi, Y.C.</au><au>Chung, P.W.</au><au>Hsieh, C.H.</au><au>Lin, C.M.</au><au>Lu, N.C.C.</au><au>Lan, S.Y.</au><au>Liu, Y.F.</au><au>Lin, M.Z.</au><au>Wang, D.W.</au><au>Tuan, H.C.</au><au>Tsai, H.H.</au><au>Lu, C.Y.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new on-chip voltage regulator for high density CMOS DRAMs</atitle><btitle>1992 Symposium on VLSI Circuits Digest of Technical Papers</btitle><stitle>VLSIC</stitle><date>1992</date><risdate>1992</risdate><spage>108</spage><epage>109</epage><pages>108-109</pages><isbn>0780307011</isbn><isbn>9780780307018</isbn><abstract>The authors report on new voltage regulator circuitry used in a 4 Mb CMOS DRAM. The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees C), while V/sub DD/ varies from 3.3 to 6.2 V. V/sub INT/ presents a positive temperature coefficient, which is adjustable, to compensate the higher cell leakage and the slowdown of MOSFET operations at higher temperature. While V/sub DD/ is raised above 6.3 V, the regulator enters the burn-in mode where V/sub INT/ follows a 2/3 V/sub DD/ curve, which gives an exact internal burn-in voltage as desired. This internal burn-in voltage is insensitive to temperature and process variations.< ></abstract><pub>IEEE</pub><doi>10.1109/VLSIC.1992.229268</doi></addata></record> |
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| identifier | ISBN: 0780307011 |
| ispartof | 1992 Symposium on VLSI Circuits Digest of Technical Papers, 1992, p.108-109 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Chaos Delay Energy consumption MOSFET circuits Power supplies Random access memory Regulators Temperature Voltage Voltage-controlled oscillators |
| title | A new on-chip voltage regulator for high density CMOS DRAMs |
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