Mobility enhancement and quantum mechanical modeling in Ge/sub x/Si/sub 1-x/ channel MOSFETs from 90 to 300 K

A peak hole inversion layer mobility of 290 cm/sup 2//V-s has been achieved at room temperature in Ge/sub x/Si/sub 1-x/ buried channel pMOSFETs. The peak mobility rises to 970 cm/sup 2//V-s at 90 K. This corresponds to a 50% enhancement in the effective mobility over Si control devices at room tempe...

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Bibliographic Details
Main Authors: Garone, P.M., Venkataraman, V., Sturn, J.C.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Capacitance
MOS devices
MOSFETs
Particle scattering
Quantum mechanics
Rough surfaces
Surface roughness
Temperature control
Voltage
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Summary:A peak hole inversion layer mobility of 290 cm/sup 2//V-s has been achieved at room temperature in Ge/sub x/Si/sub 1-x/ buried channel pMOSFETs. The peak mobility rises to 970 cm/sup 2//V-s at 90 K. This corresponds to a 50% enhancement in the effective mobility over Si control devices at room temperature and enhancements of over 100% at 90 K. The mobility of MOS-gated Ge/sub x/Si/sub 1-x/ buried channel transistors can be effectively modeled at room temperature by considering the dependence of the surface scattering on the average separation of carriers from the Si/SiO/sub 2/ interface. The mobility for devices with a 75-AA and a 105-AA Si spacer layer was tested and accurately modeled at room temperature using parameters extracted from a Si control device. At low temperatures ( approximately 90 K) an additional scattering term must be included to better fit the data. It is suggested that this additional term could result from alloy scattering in the Ge/sub x/Si/sub 1-x/ channel.< >
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.1991.235431