Electrical characterization of textured interpoly capacitors for advanced stacked DRAMs

The authors present and discuss the C-V, I-V and TDDB (time-dependent dielectric breakdown) characteristics of textured interpoly capacitors fabricated with different process conditions. It is concluded that the combination of a rough storage electrode with a dielectric that has a bulk-limited condu...

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Main Authors: Fazan, P.C., Ditali, A.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Capacitors
Dielectric breakdown
Dielectric devices
Electrodes
Manufacturing
Surfaces
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creator Fazan, P.C.
Ditali, A.
description The authors present and discuss the C-V, I-V and TDDB (time-dependent dielectric breakdown) characteristics of textured interpoly capacitors fabricated with different process conditions. It is concluded that the combination of a rough storage electrode with a dielectric that has a bulk-limited conduction offers a considerable increase in capacitance while improving device reliability. Textured stacked capacitors (TSTCs) are proposed for the manufacture of 64-Mb DRAMs. Compared to other advanced stacked capacitor concepts, the approach drastically reduces process complexity and topography.< >
doi_str_mv 10.1109/IEDM.1990.237112
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_237112</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>237112</ieee_id><sourcerecordid>237112</sourcerecordid><originalsourceid>FETCH-LOGICAL-i87t-6c7fefe3e242c87dc0295bf4736a58b69eba2c60bc4e0c648e0d45a37629cf7f3</originalsourceid><addsrcrecordid>eNotkM1Kw0AURgdRMFb34mpeIHV-kpnMsrSxFloEKeiu3NzcwdHYhMko1qe3UFdn8R2-xWHsVoqplMLdr-rFZiqdE1OlrZTqjGVKliYX0r6es0xIo3PpZHXJrsbxXQhlS1dm7KXuCFMMCB3HN4iAiWL4hRT6Pe89T_STviK1POyPw9B3B44wAIbUx5H7PnJov2GPR2NMgB9HLp5nm_GaXXjoRrr554RtH-rt_DFfPy1X89k6D5VNuUHryZMmVSisbItCubLxhdUGyqoxjhpQaESDBQk0RUWiLUrQ1iiH3no9YXen20BEuyGGT4iH3amA_gMK2FHK</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Electrical characterization of textured interpoly capacitors for advanced stacked DRAMs</title><source>IEEE Xplore All Conference Series</source><creator>Fazan, P.C. ; Ditali, A.</creator><creatorcontrib>Fazan, P.C. ; Ditali, A.</creatorcontrib><description>The authors present and discuss the C-V, I-V and TDDB (time-dependent dielectric breakdown) characteristics of textured interpoly capacitors fabricated with different process conditions. It is concluded that the combination of a rough storage electrode with a dielectric that has a bulk-limited conduction offers a considerable increase in capacitance while improving device reliability. Textured stacked capacitors (TSTCs) are proposed for the manufacture of 64-Mb DRAMs. Compared to other advanced stacked capacitor concepts, the approach drastically reduces process complexity and topography.&lt; &gt;</description><identifier>ISSN: 0163-1918</identifier><identifier>EISSN: 2156-017X</identifier><identifier>DOI: 10.1109/IEDM.1990.237112</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Capacitors ; Dielectric breakdown ; Dielectric devices ; Electrodes ; Manufacturing ; Surfaces</subject><ispartof>International Technical Digest on Electron Devices, 1990, p.663-666</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/237112$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,4050,4051,23930,23931,25140,27925,54555,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/237112$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Fazan, P.C.</creatorcontrib><creatorcontrib>Ditali, A.</creatorcontrib><title>Electrical characterization of textured interpoly capacitors for advanced stacked DRAMs</title><title>International Technical Digest on Electron Devices</title><addtitle>IEDM</addtitle><description>The authors present and discuss the C-V, I-V and TDDB (time-dependent dielectric breakdown) characteristics of textured interpoly capacitors fabricated with different process conditions. It is concluded that the combination of a rough storage electrode with a dielectric that has a bulk-limited conduction offers a considerable increase in capacitance while improving device reliability. Textured stacked capacitors (TSTCs) are proposed for the manufacture of 64-Mb DRAMs. Compared to other advanced stacked capacitor concepts, the approach drastically reduces process complexity and topography.&lt; &gt;</description><subject>Capacitance</subject><subject>Capacitors</subject><subject>Dielectric breakdown</subject><subject>Dielectric devices</subject><subject>Electrodes</subject><subject>Manufacturing</subject><subject>Surfaces</subject><issn>0163-1918</issn><issn>2156-017X</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1990</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkM1Kw0AURgdRMFb34mpeIHV-kpnMsrSxFloEKeiu3NzcwdHYhMko1qe3UFdn8R2-xWHsVoqplMLdr-rFZiqdE1OlrZTqjGVKliYX0r6es0xIo3PpZHXJrsbxXQhlS1dm7KXuCFMMCB3HN4iAiWL4hRT6Pe89T_STviK1POyPw9B3B44wAIbUx5H7PnJov2GPR2NMgB9HLp5nm_GaXXjoRrr554RtH-rt_DFfPy1X89k6D5VNuUHryZMmVSisbItCubLxhdUGyqoxjhpQaESDBQk0RUWiLUrQ1iiH3no9YXen20BEuyGGT4iH3amA_gMK2FHK</recordid><startdate>1990</startdate><enddate>1990</enddate><creator>Fazan, P.C.</creator><creator>Ditali, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1990</creationdate><title>Electrical characterization of textured interpoly capacitors for advanced stacked DRAMs</title><author>Fazan, P.C. ; Ditali, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-6c7fefe3e242c87dc0295bf4736a58b69eba2c60bc4e0c648e0d45a37629cf7f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Capacitance</topic><topic>Capacitors</topic><topic>Dielectric breakdown</topic><topic>Dielectric devices</topic><topic>Electrodes</topic><topic>Manufacturing</topic><topic>Surfaces</topic><toplevel>online_resources</toplevel><creatorcontrib>Fazan, P.C.</creatorcontrib><creatorcontrib>Ditali, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fazan, P.C.</au><au>Ditali, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Electrical characterization of textured interpoly capacitors for advanced stacked DRAMs</atitle><btitle>International Technical Digest on Electron Devices</btitle><stitle>IEDM</stitle><date>1990</date><risdate>1990</risdate><spage>663</spage><epage>666</epage><pages>663-666</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><abstract>The authors present and discuss the C-V, I-V and TDDB (time-dependent dielectric breakdown) characteristics of textured interpoly capacitors fabricated with different process conditions. It is concluded that the combination of a rough storage electrode with a dielectric that has a bulk-limited conduction offers a considerable increase in capacitance while improving device reliability. Textured stacked capacitors (TSTCs) are proposed for the manufacture of 64-Mb DRAMs. Compared to other advanced stacked capacitor concepts, the approach drastically reduces process complexity and topography.&lt; &gt;</abstract><pub>IEEE</pub><doi>10.1109/IEDM.1990.237112</doi><tpages>4</tpages></addata></record>
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identifier ISSN: 0163-1918
ispartof International Technical Digest on Electron Devices, 1990, p.663-666
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2156-017X
language eng
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source IEEE Xplore All Conference Series
subjects Capacitance
Capacitors
Dielectric breakdown
Dielectric devices
Electrodes
Manufacturing
Surfaces
title Electrical characterization of textured interpoly capacitors for advanced stacked DRAMs
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T14%3A41%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Electrical%20characterization%20of%20textured%20interpoly%20capacitors%20for%20advanced%20stacked%20DRAMs&rft.btitle=International%20Technical%20Digest%20on%20Electron%20Devices&rft.au=Fazan,%20P.C.&rft.date=1990&rft.spage=663&rft.epage=666&rft.pages=663-666&rft.issn=0163-1918&rft.eissn=2156-017X&rft_id=info:doi/10.1109/IEDM.1990.237112&rft_dat=%3Cieee_CHZPO%3E237112%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i87t-6c7fefe3e242c87dc0295bf4736a58b69eba2c60bc4e0c648e0d45a37629cf7f3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=237112&rfr_iscdi=true