Memory cell and technology issues for 64- and 256-Mbit one-transistor cell MOSD DRAMs

The memory cell and technology requirements and issues for 64- and 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. Projected requirements have been developed for key parameters such as die size, cell area, charge capacity, sto...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings of the IEEE 1989-03, Vol.77 (3), p.374-388
Main Authors: Tasch, A.F., Parker, L.H.
Format: Article
Language:English
Subjects:
Capacitance
Error analysis
Leakage current
Random access memory
Voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The memory cell and technology requirements and issues for 64- and 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. Projected requirements have been developed for key parameters such as die size, cell area, charge capacity, storage capacitance and area, leakage current, and on-current. These requirements are based on an analysis and assessment of expected improvements in soft error rate, sense amplifier sensitivity, 0-1 storage voltage difference, and bit line capacitance. Pivotal issues specific to the DRAM are identified. It is concluded that sufficient progress will be made so that 64-Mb DRAMs will be successfully produced in the early to mid-1990s.< >
ISSN:0018-9219
DOI:10.1109/5.24125