New design error modeling and metrics for design validation

When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. This produces uncertainty as to how much of the design has been verified. To provide a measure of the simulation pattern coverage based on design erro...

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Bibliographic Details
Main Authors: Kang, S., Szygenda, S.A.
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Automatic testing
Circuits
Computational modeling
Computer errors
Computer simulation
Design engineering
Digital systems
Drives
Test pattern generators
Online Access:Request full text
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Summary:When simulation is used for design verification, a subset of simulation input patterns is used, since exhaustive simulation is usually not practical. This produces uncertainty as to how much of the design has been verified. To provide a measure of the simulation pattern coverage based on design error modeling, a new simulation coverage metric is introduced. This measure is useful for obtaining insight into the actual level of design validation, since it provides more realistic results than those which are presently available.< >
DOI:10.1109/EURDAC.1992.246201