An asymmetric sidewall process for high performance LDD MOSFET's

An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no add...

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Bibliographic Details
Published in:IEEE transactions on electron devices 1994-02, Vol.41 (2), p.186-190
Main Authors: Horiuchi, T., Homma, T., Murao, Y., Okumura, K.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit optimization
CMOS process
CMOS technology
Electronics
Exact sciences and technology
Fabrication
Hot carriers
Implants
MOSFET circuits
Negative feedback
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Space technology
Transistors
Voltage
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Summary:An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined.< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.277381