A data-parallel programming model for reconfigurable architectures

Recently, several machines have been built using field programmable gate array (FPGA) technology. These reconfigurable architectures have demonstrated very high performance for a variety of problems. The configuration of these machines typically rely on some form of hardware specification. The autho...

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Bibliographic Details
Main Authors: Guccione, S.A., Gonzalez, M.J.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Computer architecture
Computer languages
Coprocessors
Field programmable gate arrays
Hardware
Microprocessors
Pipeline processing
Programming profession
Reconfigurable architectures
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Summary:Recently, several machines have been built using field programmable gate array (FPGA) technology. These reconfigurable architectures have demonstrated very high performance for a variety of problems. The configuration of these machines typically rely on some form of hardware specification. The authors demonstrate that a more traditional software approach may be used. A vector based data-parallel model and its mapping to a reconfigurable architecture are introduced. Included in the model are parallel prefix or scan operators. The language supporting this model is a subset of the C programming language.< >
DOI:10.1109/FPGA.1993.279476