Verification of circuits described in VHDL through extraction of design intent

Verification of an implementation against its specification in the design hierarchy is of paramount importance and becomes increasingly difficult with the size and complexity of the circuit. We present a comprehensive verification framework (VEHICLE) which integrates a BDD package with theorem-provi...

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Bibliographic Details
Main Authors: Hoskote, Y.V., Moondanos, J., Abraham, J.A., Fussell, D.S.
Format: Conference Proceeding
Language:English
Subjects:
Automotive engineering
Binary decision diagrams
Circuit synthesis
Computer bugs
Design engineering
Hardware design languages
Jacobian matrices
Packaging
Scheduling
Vehicles
Online Access:Request full text
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Summary:Verification of an implementation against its specification in the design hierarchy is of paramount importance and becomes increasingly difficult with the size and complexity of the circuit. We present a comprehensive verification framework (VEHICLE) which integrates a BDD package with theorem-proving techniques, and requires minimal user interaction. VEHICLE can verify VHDL designs from the scheduled behavioral level down to the gate level by capturing the design intent, on the basis of a formal semantics, in a form appropriate for input to the verifier. Results are given for the verification of several example circuits.< >
ISSN:1063-9667
2380-6923
DOI:10.1109/ICVD.1994.282730