A low-power, area-efficient digital filter for decimation and interpolation

• Published in: IEEE journal of solid-state circuits 1994-06, Vol.29 (6), p.679-687
• Main Authors: Brandt, B.P., Wooley, B.A.
• Format: Article
• Language: English
• Subjects: Analog-digital conversion; Applied sciences; CMOS logic circuits; CMOS technology; Digital arithmetic; Digital filters; Electronics; Energy consumption; Exact sciences and technology; Finite impulse response filter; Hardware; IIR filters; Integrated circuits; Integrated circuits by function (including memories and processors); Interpolation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.293113

The area and power consumption of oversampled data converters are governed largely by the associated digital decimation and interpolation filters. This paper presents a low-power, area-efficient, mask-programmable digital filter for decimation and interpolation in digital-audio applications. Several architectural and implementation features reduce the complexity of the filter and allow its realization in a die area of only 3670 mils/sup 2/ (2.37 mm/sup 2/) in a 1-/spl mu/m CMOS technology. The use of simple multiplier-free arithmetic logic and a new memory addressing scheme for multi rate digital filters results in a power consumption of only 18.8 mW from a 5-V supply and 6.5 mW from a 3-V supply. The memory addressing scheme and the programmable functionality of the filter are general enough to implement a wide class of FIR and IIR single-rate and multi-rate digital filters.< >