Predicting and precluding problems with memory latency

By examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hiera...

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Bibliographic Details
Published in:IEEE MICRO 1994-08, Vol.14 (4), p.59-67
Main Authors: Boland, K., Dollas, A.
Format: Article
Language:English
Subjects:
Application software
Boosting
Clocks
Computer memory
Content addressable storage
Delay
Microcomputers
Microprocessors
Prefetching
Random access memory
Technology
Throughput
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Summary:By examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hierarchies. We look at some of the current techniques for boosting cache performance, especially compiler-based methods for code restructuring and instruction and data prefetching. These two areas will likely yield improvements for a much larger domain of applications in the future.< >
ISSN:0272-1732
1937-4143
DOI:10.1109/40.296166