Efficient path identification for delay testing /spl minus/ time and space optimization

This paper presents an efficient method of handling a large number of paths during path-delay fault testing. Instead of handling the corresponding set of signals, an identifier is derived for every path. We handle up to three billion paths because the memory requirement is only about three bits per...

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Bibliographic Details
Main Authors: Wittman, H., Henftling, M.
Format: Conference Proceeding
Language:English
Subjects:
Automatic testing
Circuit faults
Circuit testing
Combinational circuits
Delay effects
Design optimization
Electronic equipment testing
Logic testing
Semiconductor device modeling
System testing
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Summary:This paper presents an efficient method of handling a large number of paths during path-delay fault testing. Instead of handling the corresponding set of signals, an identifier is derived for every path. We handle up to three billion paths because the memory requirement is only about three bits per path. Compared to former approaches, experimental results show fast access, small memory requirements, and negligible CPU-times for the management of huge path sets.< >
DOI:10.1109/EDTC.1994.326827