Architectural verification of processors using symbolic instruction graphs

High performance processor designs use techniques such as pipelining, multiple execution units, register renaming, bypass paths, and branch prediction to meet their goals. These techniques make them susceptible to design errors that are triggered only when executing complex sequences of instructions...

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Bibliographic Details
Main Authors: Chandra, A.K., Iyengar, V.S., Jawalekar, R.V., Mullen, M.P., Nair, I., Rosen, B.K.
Format: Conference Proceeding
Language:English
Subjects:
Character generation
Counting circuits
Engines
Pipeline processing
Process design
Registers
Resource management
State-space methods
System testing
User interfaces
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Summary:High performance processor designs use techniques such as pipelining, multiple execution units, register renaming, bypass paths, and branch prediction to meet their goals. These techniques make them susceptible to design errors that are triggered only when executing complex sequences of instructions. We introduce a language called SIGL for specifying symbolic instruction graphs (SIGs) that can be used as templates for such test cases. SIGL allows specification of constraints in a high level template from which many test cases can be generated, all targeting some specific characteristic of a processor design. SIGL has been used successfully to check the conformance of various industrial processor designs to their architectural specifications.< >
DOI:10.1109/ICCD.1994.331949