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Efficient nonblocking switching networks for interprocessor communications in multiprocessor systems
The performance of a multiprocessor system depends heavily on its ability to provide conflict free paths among its processors. In this paper, we explore the possibility of using a nonblocking network with O(N log N) edges (crosspoints) to interconnect the processors of an N processor system, We comb...
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Published in: | IEEE transactions on parallel and distributed systems 1995-02, Vol.6 (2), p.132-141 |
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container_title | IEEE transactions on parallel and distributed systems |
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creator | Fong-Chih Shao Yavuz Oruc, A. |
description | The performance of a multiprocessor system depends heavily on its ability to provide conflict free paths among its processors. In this paper, we explore the possibility of using a nonblocking network with O(N log N) edges (crosspoints) to interconnect the processors of an N processor system, We combine Bassalygo and Pinsker's implicit design of strictly nonblocking networks with an explicit construction of expanders to obtain a strictly nonblocking network with -765.18N+352.8N log N edges and 2+log(N/5) depth. We present an efficient parallel algorithm for routing connection requests on this network and implement it on three parallel processor topologies. The implementation on a parallel processor whose processing elements are interconnected as in the Bassalygo-Pinsker network requires O(N log N) processing elements, O(N log N) interprocessor links and it takes O(log N) steps to route any single connection request where each step involves a small number (/spl ap/72) of bit-level operations. A contracted or folded version of the same implementation reduces the processing element count to O(N) without increasing the link count or the routing time. Finally, we establish that the same algorithm takes O(log/sup 3/ N) steps on a perfect shuffle processor with O(N) processing elements. These results improve the crosspoint, depth and routing time complexities of the previously reported strictly nonblocking networks.< > |
doi_str_mv | 10.1109/71.342124 |
format | article |
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In this paper, we explore the possibility of using a nonblocking network with O(N log N) edges (crosspoints) to interconnect the processors of an N processor system, We combine Bassalygo and Pinsker's implicit design of strictly nonblocking networks with an explicit construction of expanders to obtain a strictly nonblocking network with -765.18N+352.8N log N edges and 2+log(N/5) depth. We present an efficient parallel algorithm for routing connection requests on this network and implement it on three parallel processor topologies. The implementation on a parallel processor whose processing elements are interconnected as in the Bassalygo-Pinsker network requires O(N log N) processing elements, O(N log N) interprocessor links and it takes O(log N) steps to route any single connection request where each step involves a small number (/spl ap/72) of bit-level operations. A contracted or folded version of the same implementation reduces the processing element count to O(N) without increasing the link count or the routing time. Finally, we establish that the same algorithm takes O(log/sup 3/ N) steps on a perfect shuffle processor with O(N) processing elements. These results improve the crosspoint, depth and routing time complexities of the previously reported strictly nonblocking networks.< ></description><identifier>ISSN: 1045-9219</identifier><identifier>EISSN: 1558-2183</identifier><identifier>DOI: 10.1109/71.342124</identifier><identifier>CODEN: ITDSEO</identifier><language>eng</language><publisher>Los Alamitos, CA: IEEE</publisher><subject>Applied sciences ; Bandwidth ; Communication switching ; Computer science; control theory; systems ; Computer systems and distributed systems. User interface ; Exact sciences and technology ; Fasteners ; Graph theory ; Intelligent networks ; Multiprocessing systems ; Network topology ; Parallel algorithms ; Routing ; Software ; Software engineering ; Telecommunications ; Telecommunications and information theory ; Teleprocessing networks. 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In this paper, we explore the possibility of using a nonblocking network with O(N log N) edges (crosspoints) to interconnect the processors of an N processor system, We combine Bassalygo and Pinsker's implicit design of strictly nonblocking networks with an explicit construction of expanders to obtain a strictly nonblocking network with -765.18N+352.8N log N edges and 2+log(N/5) depth. We present an efficient parallel algorithm for routing connection requests on this network and implement it on three parallel processor topologies. The implementation on a parallel processor whose processing elements are interconnected as in the Bassalygo-Pinsker network requires O(N log N) processing elements, O(N log N) interprocessor links and it takes O(log N) steps to route any single connection request where each step involves a small number (/spl ap/72) of bit-level operations. A contracted or folded version of the same implementation reduces the processing element count to O(N) without increasing the link count or the routing time. Finally, we establish that the same algorithm takes O(log/sup 3/ N) steps on a perfect shuffle processor with O(N) processing elements. These results improve the crosspoint, depth and routing time complexities of the previously reported strictly nonblocking networks.< ></description><subject>Applied sciences</subject><subject>Bandwidth</subject><subject>Communication switching</subject><subject>Computer science; control theory; systems</subject><subject>Computer systems and distributed systems. User interface</subject><subject>Exact sciences and technology</subject><subject>Fasteners</subject><subject>Graph theory</subject><subject>Intelligent networks</subject><subject>Multiprocessing systems</subject><subject>Network topology</subject><subject>Parallel algorithms</subject><subject>Routing</subject><subject>Software</subject><subject>Software engineering</subject><subject>Telecommunications</subject><subject>Telecommunications and information theory</subject><subject>Teleprocessing networks. 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User interface</topic><topic>Exact sciences and technology</topic><topic>Fasteners</topic><topic>Graph theory</topic><topic>Intelligent networks</topic><topic>Multiprocessing systems</topic><topic>Network topology</topic><topic>Parallel algorithms</topic><topic>Routing</topic><topic>Software</topic><topic>Software engineering</topic><topic>Telecommunications</topic><topic>Telecommunications and information theory</topic><topic>Teleprocessing networks. Isdn</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Fong-Chih Shao</creatorcontrib><creatorcontrib>Yavuz Oruc, A.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on parallel and distributed systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Fong-Chih Shao</au><au>Yavuz Oruc, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Efficient nonblocking switching networks for interprocessor communications in multiprocessor systems</atitle><jtitle>IEEE transactions on parallel and distributed systems</jtitle><stitle>TPDS</stitle><date>1995-02-01</date><risdate>1995</risdate><volume>6</volume><issue>2</issue><spage>132</spage><epage>141</epage><pages>132-141</pages><issn>1045-9219</issn><eissn>1558-2183</eissn><coden>ITDSEO</coden><abstract>The performance of a multiprocessor system depends heavily on its ability to provide conflict free paths among its processors. In this paper, we explore the possibility of using a nonblocking network with O(N log N) edges (crosspoints) to interconnect the processors of an N processor system, We combine Bassalygo and Pinsker's implicit design of strictly nonblocking networks with an explicit construction of expanders to obtain a strictly nonblocking network with -765.18N+352.8N log N edges and 2+log(N/5) depth. We present an efficient parallel algorithm for routing connection requests on this network and implement it on three parallel processor topologies. The implementation on a parallel processor whose processing elements are interconnected as in the Bassalygo-Pinsker network requires O(N log N) processing elements, O(N log N) interprocessor links and it takes O(log N) steps to route any single connection request where each step involves a small number (/spl ap/72) of bit-level operations. A contracted or folded version of the same implementation reduces the processing element count to O(N) without increasing the link count or the routing time. Finally, we establish that the same algorithm takes O(log/sup 3/ N) steps on a perfect shuffle processor with O(N) processing elements. These results improve the crosspoint, depth and routing time complexities of the previously reported strictly nonblocking networks.< ></abstract><cop>Los Alamitos, CA</cop><pub>IEEE</pub><doi>10.1109/71.342124</doi><tpages>10</tpages><oa>free_for_read</oa></addata></record> |
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subjects | Applied sciences Bandwidth Communication switching Computer science control theory systems Computer systems and distributed systems. User interface Exact sciences and technology Fasteners Graph theory Intelligent networks Multiprocessing systems Network topology Parallel algorithms Routing Software Software engineering Telecommunications Telecommunications and information theory Teleprocessing networks. Isdn |
title | Efficient nonblocking switching networks for interprocessor communications in multiprocessor systems |
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