Multiplier-free realization for decimators in /spl Sigma//spl Delta/ A/D converters

We propose a multiplier-free realization for the decimation process in sigma-delta, analog/digital converters. The decimation is realized by multiplier-free comb filter and multiplier-free FIR filter, with appropriate downsampling. The realization uses periodically time-varying (PTV) coefficients an...

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Bibliographic Details
Main Authors: Tantaratana, S., Ghanekar, S.P., Jianlin Li
Format: Conference Proceeding
Language:English
Subjects:
Analog-digital conversion
Delta-sigma modulation
Finite impulse response filter
Hardware
Very large scale integration
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Description
Summary:We propose a multiplier-free realization for the decimation process in sigma-delta, analog/digital converters. The decimation is realized by multiplier-free comb filter and multiplier-free FIR filter, with appropriate downsampling. The realization uses periodically time-varying (PTV) coefficients and modulators to reduce the hardware. It has a simple structure and easy to implement in VLSI. The coefficients in the realization belong to either the ternary set (0, /spl plusmn/1) or the quinary set (0, /spl plusmn/1, /spl plusmn/2).< >
ISSN:1058-6393
2576-2303
DOI:10.1109/ACSSC.1993.342381