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A highly-parallel architecture for concurrent rule match of AI production systems
In this paper, a highly-parallel architecture for concurrent rule match is proposed to speed up the execution time of match process of AI production systems. The architecture fully exploits the advantages of content addressable memory (CAM) not only to buffer the database of current assertions, call...
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container_end_page | 691 vol.2 |
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creator | Chie Dou |
description | In this paper, a highly-parallel architecture for concurrent rule match is proposed to speed up the execution time of match process of AI production systems. The architecture fully exploits the advantages of content addressable memory (CAM) not only to buffer the database of current assertions, called the working memory (WM), but also to support the functions of parallelly evaluating interconditions among patterns of productions. The architecture first compiles the left-hand side (LHS) of each production into a symbolic form and then assigns a CAM cell array, called CAM block, to each production for buffering elements as well as evaluating interconditions. The set of productions that are affected during a match cycle can be evaluated concurrently and independently within their own CAM blocks. Due to the uniformity of constructing arrays of processing elements by CAM block, the novel architecture is suitable for VLSI implementation. The analysis of the expected performance indicates that the novel architecture might speed up conventional forward-chaining production systems by perhaps a factor of 100 or higher.< > |
doi_str_mv | 10.1109/TENCON.1994.369217 |
format | conference_proceeding |
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The architecture fully exploits the advantages of content addressable memory (CAM) not only to buffer the database of current assertions, called the working memory (WM), but also to support the functions of parallelly evaluating interconditions among patterns of productions. The architecture first compiles the left-hand side (LHS) of each production into a symbolic form and then assigns a CAM cell array, called CAM block, to each production for buffering elements as well as evaluating interconditions. The set of productions that are affected during a match cycle can be evaluated concurrently and independently within their own CAM blocks. Due to the uniformity of constructing arrays of processing elements by CAM block, the novel architecture is suitable for VLSI implementation. The analysis of the expected performance indicates that the novel architecture might speed up conventional forward-chaining production systems by perhaps a factor of 100 or higher.< ></description><identifier>ISBN: 0780318625</identifier><identifier>ISBN: 9780780318625</identifier><identifier>DOI: 10.1109/TENCON.1994.369217</identifier><language>eng</language><publisher>IEEE</publisher><subject>Artificial intelligence ; CADCAM ; Computer aided manufacturing ; Computer architecture ; Knowledge based systems ; Parallel processing ; Performance analysis ; Production systems ; Very large scale integration</subject><ispartof>Proceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology', 1994, p.687-691 vol.2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/369217$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/369217$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chie Dou</creatorcontrib><title>A highly-parallel architecture for concurrent rule match of AI production systems</title><title>Proceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology'</title><addtitle>TENCON</addtitle><description>In this paper, a highly-parallel architecture for concurrent rule match is proposed to speed up the execution time of match process of AI production systems. The architecture fully exploits the advantages of content addressable memory (CAM) not only to buffer the database of current assertions, called the working memory (WM), but also to support the functions of parallelly evaluating interconditions among patterns of productions. The architecture first compiles the left-hand side (LHS) of each production into a symbolic form and then assigns a CAM cell array, called CAM block, to each production for buffering elements as well as evaluating interconditions. The set of productions that are affected during a match cycle can be evaluated concurrently and independently within their own CAM blocks. Due to the uniformity of constructing arrays of processing elements by CAM block, the novel architecture is suitable for VLSI implementation. The analysis of the expected performance indicates that the novel architecture might speed up conventional forward-chaining production systems by perhaps a factor of 100 or higher.< ></description><subject>Artificial intelligence</subject><subject>CADCAM</subject><subject>Computer aided manufacturing</subject><subject>Computer architecture</subject><subject>Knowledge based systems</subject><subject>Parallel processing</subject><subject>Performance analysis</subject><subject>Production systems</subject><subject>Very large scale integration</subject><isbn>0780318625</isbn><isbn>9780780318625</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1994</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj8tqwzAUBQWl0DbND2SlH7ArWS9raUzaBkJCIF0HWb2qXeQHkrzw39eQzubshjMI7SjJKSX67bo_1edTTrXmOZO6oOoBvRBVEkZLWYgntI3xl6xwQRRlz-hS4bb7af2STSYY78FjE2zbJbBpDoDdGLAdBzuHAEPCYfaAe5Nsi0eHqwOewvg929SNA45LTNDHV_TojI-w_d8N-nrfX-vP7Hj-ONTVMeso4SmzVkkJRJJGakkYCCFFIYlrrONCcbW-bbjmBS2Fso3l3AonlNElCOBsZYN2d28HALcpdL0Jy-0ezf4AysNNXA</recordid><startdate>1994</startdate><enddate>1994</enddate><creator>Chie Dou</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1994</creationdate><title>A highly-parallel architecture for concurrent rule match of AI production systems</title><author>Chie Dou</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-cc766e060b69603e5565260fbcf45747625b49421857cbc44c5f57a98e5e43333</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1994</creationdate><topic>Artificial intelligence</topic><topic>CADCAM</topic><topic>Computer aided manufacturing</topic><topic>Computer architecture</topic><topic>Knowledge based systems</topic><topic>Parallel processing</topic><topic>Performance analysis</topic><topic>Production systems</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Chie Dou</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chie Dou</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A highly-parallel architecture for concurrent rule match of AI production systems</atitle><btitle>Proceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology'</btitle><stitle>TENCON</stitle><date>1994</date><risdate>1994</risdate><spage>687</spage><epage>691 vol.2</epage><pages>687-691 vol.2</pages><isbn>0780318625</isbn><isbn>9780780318625</isbn><abstract>In this paper, a highly-parallel architecture for concurrent rule match is proposed to speed up the execution time of match process of AI production systems. The architecture fully exploits the advantages of content addressable memory (CAM) not only to buffer the database of current assertions, called the working memory (WM), but also to support the functions of parallelly evaluating interconditions among patterns of productions. The architecture first compiles the left-hand side (LHS) of each production into a symbolic form and then assigns a CAM cell array, called CAM block, to each production for buffering elements as well as evaluating interconditions. The set of productions that are affected during a match cycle can be evaluated concurrently and independently within their own CAM blocks. Due to the uniformity of constructing arrays of processing elements by CAM block, the novel architecture is suitable for VLSI implementation. The analysis of the expected performance indicates that the novel architecture might speed up conventional forward-chaining production systems by perhaps a factor of 100 or higher.< ></abstract><pub>IEEE</pub><doi>10.1109/TENCON.1994.369217</doi></addata></record> |
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identifier | ISBN: 0780318625 |
ispartof | Proceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology', 1994, p.687-691 vol.2 |
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language | eng |
recordid | cdi_ieee_primary_369217 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Artificial intelligence CADCAM Computer aided manufacturing Computer architecture Knowledge based systems Parallel processing Performance analysis Production systems Very large scale integration |
title | A highly-parallel architecture for concurrent rule match of AI production systems |
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