An analog VLSI neural network architecture with on-chip learning

A user-configurable analog VLSI feedforward neural network architecture that adds only 10% to chip area relative to a fixed topology is described. Central to the architecture is a novel synapse circuit that consumes 4500 /spl mu/m/sup 2/ in a 2-/spl mu/m technology. Hybrid dynamic and non-volatile w...

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Bibliographic Details
Main Authors: Montalvo, A.J., Paulos, J.J., Gyurcsik, R.S.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Computer architecture
Feedforward neural networks
Network-on-a-chip
Neural networks
Neurons
Nonvolatile memory
Semiconductor device measurement
Very large scale integration
Voltage
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Summary:A user-configurable analog VLSI feedforward neural network architecture that adds only 10% to chip area relative to a fixed topology is described. Central to the architecture is a novel synapse circuit that consumes 4500 /spl mu/m/sup 2/ in a 2-/spl mu/m technology. Hybrid dynamic and non-volatile weight storage allows fast learning as well as reliable long-term storage. Measured synapse current-voltage curves from a test chip are presented. The synapse includes a weight increment circuit that adds offset of only 1 part in 13 bits allowing analog-domain on-chip learning. Weight update circuits that implement a semiparallel weight perturbation learning algorithm are presented.< >
DOI:10.1109/ICNN.1994.374484