BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

• Main Authors: Sung, J.M., Chui, T.Y., Lau, K., Lui, T.M., Archer, V.D., Razavi, B., Swartz, R.G., Erceg, F.M., Glick, J.T., Hower, G.R., Krafty, S.A., LaDuca, A.J., Ling, M.P., Moerschel, K.G., Possanza, W.A., Prozonic, M.A., Long, T.P.
• Format: Conference Proceeding
• Language: English
• Subjects: BiCMOS integrated circuits; Capacitance; Current measurement; Delay; Energy consumption; Fabrication; Isolation technology; Microelectronics; Power supplies; Process design
• DOI: 10.1109/CICC.1994.379776

We present AT&T BEST2 a high performance BiCMOS technology designed for supporting low-power multi-GHz mixed-signal applications. Processing modules reported include novel device structure fabrication, selective-epitaxy-capping of As buried layer, and deep fully-recessed LOCOS isolation. The developed process with relaxed design rules has achieved f/sub t/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 um/sup 2/) or 23 GHz and 24 GHz at V/sub ce/=3 V, respectively. With BV/sub ceo//spl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical/minimum ECL gate delays are measured 48 ps/37 ps (A/sub e/=1/spl times/2 um/sup 2/: 500 mV swing) at 0.6 mA/2.1 mA stage current, and CMOS gate delay (gate oxide=125 A/spl deg/, L/sub eff/=0.6 um; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. BiCMOS phase-locked-loop (emitter width=1 um; gate L/sub eff/=0.7 um) has achieved a world record of 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< >