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BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications
We present AT&T BEST2 a high performance BiCMOS technology designed for supporting low-power multi-GHz mixed-signal applications. Processing modules reported include novel device structure fabrication, selective-epitaxy-capping of As buried layer, and deep fully-recessed LOCOS isolation. The dev...
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| creator | Sung, J.M. Chui, T.Y. Lau, K. Lui, T.M. Archer, V.D. Razavi, B. Swartz, R.G. Erceg, F.M. Glick, J.T. Hower, G.R. Krafty, S.A. LaDuca, A.J. Ling, M.P. Moerschel, K.G. Possanza, W.A. Prozonic, M.A. Long, T.P. |
| description | We present AT&T BEST2 a high performance BiCMOS technology designed for supporting low-power multi-GHz mixed-signal applications. Processing modules reported include novel device structure fabrication, selective-epitaxy-capping of As buried layer, and deep fully-recessed LOCOS isolation. The developed process with relaxed design rules has achieved f/sub t/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 um/sup 2/) or 23 GHz and 24 GHz at V/sub ce/=3 V, respectively. With BV/sub ceo//spl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical/minimum ECL gate delays are measured 48 ps/37 ps (A/sub e/=1/spl times/2 um/sup 2/: 500 mV swing) at 0.6 mA/2.1 mA stage current, and CMOS gate delay (gate oxide=125 A/spl deg/, L/sub eff/=0.6 um; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. BiCMOS phase-locked-loop (emitter width=1 um; gate L/sub eff/=0.7 um) has achieved a world record of 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< > |
| doi_str_mv | 10.1109/CICC.1994.379776 |
| format | conference_proceeding |
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Processing modules reported include novel device structure fabrication, selective-epitaxy-capping of As buried layer, and deep fully-recessed LOCOS isolation. The developed process with relaxed design rules has achieved f/sub t/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 um/sup 2/) or 23 GHz and 24 GHz at V/sub ce/=3 V, respectively. With BV/sub ceo//spl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical/minimum ECL gate delays are measured 48 ps/37 ps (A/sub e/=1/spl times/2 um/sup 2/: 500 mV swing) at 0.6 mA/2.1 mA stage current, and CMOS gate delay (gate oxide=125 A/spl deg/, L/sub eff/=0.6 um; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. BiCMOS phase-locked-loop (emitter width=1 um; gate L/sub eff/=0.7 um) has achieved a world record of 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< ></description><identifier>ISBN: 0780318862</identifier><identifier>ISBN: 9780780318861</identifier><identifier>DOI: 10.1109/CICC.1994.379776</identifier><language>eng</language><publisher>IEEE</publisher><subject>BiCMOS integrated circuits ; Capacitance ; Current measurement ; Delay ; Energy consumption ; Fabrication ; Isolation technology ; Microelectronics ; Power supplies ; Process design</subject><ispartof>Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94, 1994, p.15-18</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/379776$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/379776$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sung, J.M.</creatorcontrib><creatorcontrib>Chui, T.Y.</creatorcontrib><creatorcontrib>Lau, K.</creatorcontrib><creatorcontrib>Lui, T.M.</creatorcontrib><creatorcontrib>Archer, V.D.</creatorcontrib><creatorcontrib>Razavi, B.</creatorcontrib><creatorcontrib>Swartz, R.G.</creatorcontrib><creatorcontrib>Erceg, F.M.</creatorcontrib><creatorcontrib>Glick, J.T.</creatorcontrib><creatorcontrib>Hower, G.R.</creatorcontrib><creatorcontrib>Krafty, S.A.</creatorcontrib><creatorcontrib>LaDuca, A.J.</creatorcontrib><creatorcontrib>Ling, M.P.</creatorcontrib><creatorcontrib>Moerschel, K.G.</creatorcontrib><creatorcontrib>Possanza, W.A.</creatorcontrib><creatorcontrib>Prozonic, M.A.</creatorcontrib><creatorcontrib>Long, T.P.</creatorcontrib><title>BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications</title><title>Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94</title><addtitle>CICC</addtitle><description>We present AT&T BEST2 a high performance BiCMOS technology designed for supporting low-power multi-GHz mixed-signal applications. Processing modules reported include novel device structure fabrication, selective-epitaxy-capping of As buried layer, and deep fully-recessed LOCOS isolation. The developed process with relaxed design rules has achieved f/sub t/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 um/sup 2/) or 23 GHz and 24 GHz at V/sub ce/=3 V, respectively. With BV/sub ceo//spl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical/minimum ECL gate delays are measured 48 ps/37 ps (A/sub e/=1/spl times/2 um/sup 2/: 500 mV swing) at 0.6 mA/2.1 mA stage current, and CMOS gate delay (gate oxide=125 A/spl deg/, L/sub eff/=0.6 um; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. BiCMOS phase-locked-loop (emitter width=1 um; gate L/sub eff/=0.7 um) has achieved a world record of 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< ></description><subject>BiCMOS integrated circuits</subject><subject>Capacitance</subject><subject>Current measurement</subject><subject>Delay</subject><subject>Energy consumption</subject><subject>Fabrication</subject><subject>Isolation technology</subject><subject>Microelectronics</subject><subject>Power supplies</subject><subject>Process design</subject><isbn>0780318862</isbn><isbn>9780780318861</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1994</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9j81qwzAQhAWl0L_cS0_7AnKkuI7sa0RKewg9JOQahLO2t8iWkFQcP0Nfui7tuXMZZgY-GMYepcikFNVSv2mdyap6znJVKbW-YndClSKXZble3bBFjB9iVlGUslC37Guz3R9W3EBHbQceQ-NCb4YaIX7OCSLahhtL7YBnyOG4LOAIG9K79z0krLvBWddOMFLqAC8pYI92AutG8CaYSInqCDPzp-LejTOypwueeZyRxoLx3lJtErkhPrDrxtiIiz-_Z08v24N-5YSIJx-oN2E6_d7K_x2_AXF_Uuk</recordid><startdate>1994</startdate><enddate>1994</enddate><creator>Sung, J.M.</creator><creator>Chui, T.Y.</creator><creator>Lau, K.</creator><creator>Lui, T.M.</creator><creator>Archer, V.D.</creator><creator>Razavi, B.</creator><creator>Swartz, R.G.</creator><creator>Erceg, F.M.</creator><creator>Glick, J.T.</creator><creator>Hower, G.R.</creator><creator>Krafty, S.A.</creator><creator>LaDuca, A.J.</creator><creator>Ling, M.P.</creator><creator>Moerschel, K.G.</creator><creator>Possanza, W.A.</creator><creator>Prozonic, M.A.</creator><creator>Long, T.P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1994</creationdate><title>BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications</title><author>Sung, J.M. ; Chui, T.Y. ; Lau, K. ; Lui, T.M. ; Archer, V.D. ; Razavi, B. ; Swartz, R.G. ; Erceg, F.M. ; Glick, J.T. ; Hower, G.R. ; Krafty, S.A. ; LaDuca, A.J. ; Ling, M.P. ; Moerschel, K.G. ; Possanza, W.A. ; Prozonic, M.A. ; Long, T.P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_3797763</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1994</creationdate><topic>BiCMOS integrated circuits</topic><topic>Capacitance</topic><topic>Current measurement</topic><topic>Delay</topic><topic>Energy consumption</topic><topic>Fabrication</topic><topic>Isolation technology</topic><topic>Microelectronics</topic><topic>Power supplies</topic><topic>Process design</topic><toplevel>online_resources</toplevel><creatorcontrib>Sung, J.M.</creatorcontrib><creatorcontrib>Chui, T.Y.</creatorcontrib><creatorcontrib>Lau, K.</creatorcontrib><creatorcontrib>Lui, T.M.</creatorcontrib><creatorcontrib>Archer, V.D.</creatorcontrib><creatorcontrib>Razavi, B.</creatorcontrib><creatorcontrib>Swartz, R.G.</creatorcontrib><creatorcontrib>Erceg, F.M.</creatorcontrib><creatorcontrib>Glick, J.T.</creatorcontrib><creatorcontrib>Hower, G.R.</creatorcontrib><creatorcontrib>Krafty, S.A.</creatorcontrib><creatorcontrib>LaDuca, A.J.</creatorcontrib><creatorcontrib>Ling, M.P.</creatorcontrib><creatorcontrib>Moerschel, K.G.</creatorcontrib><creatorcontrib>Possanza, W.A.</creatorcontrib><creatorcontrib>Prozonic, M.A.</creatorcontrib><creatorcontrib>Long, T.P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sung, J.M.</au><au>Chui, T.Y.</au><au>Lau, K.</au><au>Lui, T.M.</au><au>Archer, V.D.</au><au>Razavi, B.</au><au>Swartz, R.G.</au><au>Erceg, F.M.</au><au>Glick, J.T.</au><au>Hower, G.R.</au><au>Krafty, S.A.</au><au>LaDuca, A.J.</au><au>Ling, M.P.</au><au>Moerschel, K.G.</au><au>Possanza, W.A.</au><au>Prozonic, M.A.</au><au>Long, T.P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications</atitle><btitle>Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94</btitle><stitle>CICC</stitle><date>1994</date><risdate>1994</risdate><spage>15</spage><epage>18</epage><pages>15-18</pages><isbn>0780318862</isbn><isbn>9780780318861</isbn><abstract>We present AT&T BEST2 a high performance BiCMOS technology designed for supporting low-power multi-GHz mixed-signal applications. Processing modules reported include novel device structure fabrication, selective-epitaxy-capping of As buried layer, and deep fully-recessed LOCOS isolation. The developed process with relaxed design rules has achieved f/sub t/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 um/sup 2/) or 23 GHz and 24 GHz at V/sub ce/=3 V, respectively. With BV/sub ceo//spl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical/minimum ECL gate delays are measured 48 ps/37 ps (A/sub e/=1/spl times/2 um/sup 2/: 500 mV swing) at 0.6 mA/2.1 mA stage current, and CMOS gate delay (gate oxide=125 A/spl deg/, L/sub eff/=0.6 um; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. BiCMOS phase-locked-loop (emitter width=1 um; gate L/sub eff/=0.7 um) has achieved a world record of 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< ></abstract><pub>IEEE</pub><doi>10.1109/CICC.1994.379776</doi></addata></record> |
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| identifier | ISBN: 0780318862 |
| ispartof | Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94, 1994, p.15-18 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | BiCMOS integrated circuits Capacitance Current measurement Delay Energy consumption Fabrication Isolation technology Microelectronics Power supplies Process design |
| title | BEST2-a high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications |
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