VERTEX: VERification of Transistor-level circuits based on model EXtraction

VERTEX, a program that performs formal verification of synchronous sequential circuits that are characterized at the transistor-level is described. Additionally, VERTEX can compare gate-level designs or Boolean specifications against their switch-level implementations. VERTEX verifies a hardware des...

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Main Authors: Moondanos, J., Wehbeh, J.A., Abrahamn, J.A., Saab, D.G.
Format: Conference Proceeding
Language:English
Subjects:
Automata
Contracts
Formal verification
Hardware
High performance computing
Manufacturing processes
Reliability engineering
Sequential circuits
Switching circuits
Very large scale integration
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creator Moondanos, J.
Wehbeh, J.A.
Abrahamn, J.A.
Saab, D.G.
description VERTEX, a program that performs formal verification of synchronous sequential circuits that are characterized at the transistor-level is described. Additionally, VERTEX can compare gate-level designs or Boolean specifications against their switch-level implementations. VERTEX verifies a hardware design by employing novel techniques to extract the relevant state variables of a switch-level circuit and to compare the finite state machine descriptions of hardware designs based on formal methods for the verification of sequential circuits.< >
doi_str_mv 10.1109/EDAC.1993.386491
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identifier ISBN: 9780818634109
ispartof 1993 European Conference on Design Automation with the European Event in ASIC Design, 1993, p.111-115
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Automata
Contracts
Formal verification
Hardware
High performance computing
Manufacturing processes
Reliability engineering
Sequential circuits
Switching circuits
Very large scale integration
title VERTEX: VERification of Transistor-level circuits based on model EXtraction
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