CMOS overcurrent test: BIC-monitor design, circuit partitioning and test patterns

The successful implementation of built-in current monitoring circuitry is the key to the practical applicability of defect-oriented CMOS test via current effects. However, inherent constraints due to dynamic effects and the overhead for large chips are still open problems. This paper introduces a no...

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Bibliographic Details
Main Authors: Vierhaus, H.T., Muhlack, L., Glaser, U.
Format: Conference Proceeding
Language:English
Subjects:
Bipolar transistors
Circuit faults
Circuit testing
CMOS technology
Delay effects
Impedance
Monitoring
Proposals
System testing
Voltage
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Summary:The successful implementation of built-in current monitoring circuitry is the key to the practical applicability of defect-oriented CMOS test via current effects. However, inherent constraints due to dynamic effects and the overhead for large chips are still open problems. This paper introduces a novel current monitor design, provides guidelines for circuit partitioning into current-monitor blocks and gives realistic numbers of test patterns for current-versus voltage test.< >
DOI:10.1109/EURMIC.1994.390380