A configurable CMOS multiplier/divider for analog VLSI

The design of a simple CMOS operational-amplifier-based multiplier/divider is presented. The 2 operational amplifier and 6 MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuit in analog signal processing are discussed. The multi...

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Bibliographic Details
Main Authors: Ismail, M., Brannen, R., Takagi, S., Khan, R., Aaserud, O., Fujii, N., Khachab, N.
Format: Conference Proceeding
Language:English
Subjects:
Analog computers
Bandwidth
Biomedical signal processing
Clocks
CMOS technology
Impedance matching
MOSFET circuits
Parasitic capacitance
Very large scale integration
Voltage control
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Summary:The design of a simple CMOS operational-amplifier-based multiplier/divider is presented. The 2 operational amplifier and 6 MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuit in analog signal processing are discussed. The multiplier/divider circuit is insensitive to MOS intrinsic parasitic capacitances. It is sensitive to operational amplifier finite unity-gain bandwidth. This sensitivity may be mitigated using the configurability property of the circuit. Experimental results are provided to support some of the theoretical claims.< >
DOI:10.1109/ISCAS.1993.393923