Automatic generation of transistor stacks for CMOS analog layout

A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constr...

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Bibliographic Details
Main Authors: Liberali, V., Malavasi, E., Pandini, D.
Format: Conference Proceeding
Language:English
Subjects:
Analog circuits
Automatic control
Circuit simulation
Constraint optimization
Cost function
Humans
Minimization
MOSFETs
Routing
Sensitivity analysis
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Description
Summary:A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function accounting for parasitic control and area optimization.< >
DOI:10.1109/ISCAS.1993.394170