GENES IV: A bit-serial processing element for a built-model neural-network accelerator

A systolic array of dedicated processing elements (PEs) is presented as the heart of a multimodel of several widely-used neural models, including multilayer perceptrons with the backpropagation learning rule and Kohonen feature maps. Each PE holds an element of the synaptic weight matrix. An instant...

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Bibliographic Details
Main Authors: Ienne, P., Viredaz, M.A.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Algorithm design and analysis
Backpropagation
Circuit testing
Hardware
Heart
Laboratories
Neural networks
Neurons
Performance evaluation
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Summary:A systolic array of dedicated processing elements (PEs) is presented as the heart of a multimodel of several widely-used neural models, including multilayer perceptrons with the backpropagation learning rule and Kohonen feature maps. Each PE holds an element of the synaptic weight matrix. An instantaneous swapping mechanism of the weight matrix allows the implementation of neural networks larger than the physical PE array. A systolically-flowing instruction accompanies each input vector propagating in the array. This avoids the need of emptying and refilling the array when the operating mode of the array is changed. Both the GENES-IV chip, containing a matrix of 2 /spl times/ 2 PEs, and an auxiliary arithmetic circuit have been manufactured and successfully tested. The MANTRA I machine has been built around these chips. Peak performances of the full system are between 200 and 400 MCPS in the evolution phase and between 100 and 200 MCUPS during the learning phase (depending on the algorithm being implemented).< >
ISSN:1063-6862
DOI:10.1109/ASAP.1993.397157