Millisecond Anneal and Short-Channel Effect Control in Si CMOS Transistor Performance

• Published in: IEEE electron device letters 2006-12, Vol.27 (12), p.969-971
• Main Authors: Nieh, C.F., Ku, K.C., Chen, C.H., Chang, H., Wang, L.T., Huang, L.P., Sheu, Y.M., Wang, C.C., Lee, T.L., Chen, S.C., Liang, M.S., Gong, J.
• Format: Article
• Language: English
• Subjects: Annealing; Applied sciences; Boron; CMOS; CMOS technology; Compound structure devices; Crystal structure; Design. Technologies. Operation analysis. Testing; Devices; Electronics; Exact sciences and technology; Fabrication; Implants; Integrated circuits; MOS devices; P-n junctions; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; short-channel effect (SCE); Silicon; Solids; Spikes; Temperature; Transistors; ultrashallow junction (USJ)
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2006.886317

In this letter, the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices are studied. The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology