High Performance VLSI Architecture Design for H.264 CAVLC Decoder

• Main Authors: Alle, M., Biswas, J., Nandy, S.K.
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; CMOS technology; Data compression; Decoding; Frequency; Libraries; Pipeline processing; Throughput; Very large scale integration; Video compression
• ISSN: 1063-6862
• DOI: 10.1109/ASAP.2006.36

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in baseline profile. In this paper, the authors describe a novel architecture for CAVLC decoder, including coeff_token decoder, level decoder, total_zeros decoder and run_before decoder. UMC library in 0.13mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with (Chang et al., 2005). Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with (Chang et al., 2005) clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to (Chang et al., 2005). The authors obtain a throughput of 1.73 * 10 6 macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD video at 30frames/seconds