Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarize...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2006-12, Vol.53 (12), p.2637-2646
Main Authors: Zhuoyuan Li, Hong, X., Qiang Zhou, Cai, Y., Bian, J., Yang, H.H., Pitchumani, V., Chung-Kuan Cheng
Format: Article
Language:English
Subjects:
Algorithms
Circuits
Complexity
Computer-aided design (CAD)
Delay
Design engineering
Design optimization
Electronic design automation and methodology
Energy consumption
Engine blocks
Engines
Heuristic
Integrated circuit interconnections
integrated_circuit_layout
Large scale integration
Optimization
Power system interconnection
Simulated annealing
Solution space
Studies
Very large scale integration
very large-scale integration (VLSI)
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Summary:Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design
ISSN:1549-8328
1057-7122
1558-0806
DOI:10.1109/TCSI.2006.883857