Cycle-accurate Verification of AHB-based RTL IP with Transaction-level System Environment

This paper presents cycle-accurate mixed-level simulation and acceleration method. This enables us to utilize transaction-level test vectors which are usually already implemented in early design steps and which are also easy to generate than HDL test vectors, to verify RTL design. As there is no com...

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Bibliographic Details
Main Authors: Heejun Shim, Sang-Heon Lee, Yun-Sik Woo, Moo-Kyoung Chung, Jae-Gon Lee, Chong-Min Kyung
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Circuit simulation
Delay
Embedded system
Hardware design languages
Integrated circuit modeling
Master-slave
Performance analysis
Software performance
Testing
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Summary:This paper presents cycle-accurate mixed-level simulation and acceleration method. This enables us to utilize transaction-level test vectors which are usually already implemented in early design steps and which are also easy to generate than HDL test vectors, to verify RTL design. As there is no commercial simulation environment that can efficiently handle transaction-level and RTL models at the same time, we employed two simulators for each abstraction-level modeling. To translate abstraction levels of communication between the two simulators, we implemented transactor that is inserted between them. This paper shows the principle of operation of the transactor focusing on the synchronization between transaction-level simulator and RTL simulator. In addition, we replaced RTL simulator with hardware accelerator to improve simulation performance. We implemented wrapper for hiding access routines of hardware acceleration from transaction-level simulator which is attached to the above mentioned transactor
DOI:10.1109/VDAT.2006.258143