Gb/s CMOS 1-4th-rate CDR with Frequency Detector and Skew calibration

A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4 th -rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4 th -rate clock architecture, the coil-free oscillator can have lower operation frequency providing s...

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Bibliographic Details
Main Authors: Tontisirin, S., Tielert, R.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Bit error rate
Calibration
Circuits
Clocks
CMOS technology
Detectors
Frequency
Jitter
Voltage-controlled oscillators
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Summary:A 1-2.25 Gb/s clock and data recovery (CDR) circuit using 1/4 th -rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4 th -rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4 th -rate CDR is implemented in standard 0.18mum CMOS technology. It has an active area of 0.7 mm 2 and consumes 100mW at 1.8V supply. The CDR has low jitter operation in a wide frequency range from 1-2.25 Gb/s. Measurement of bit-error rate is less than 10 -12 for 2.25 Gb/s incoming data 2 7 -1 PRBS, jitter peak-to-peak of 0.7 unit interval(UI) modulation at 10 MHz
DOI:10.1109/VDAT.2006.258156