Design of Reconfigurable Low-Power Pipelined Array Multiplier

Energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth i...

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Bibliographic Details
Main Authors: Jiun-Ping Wang, Shiann-Rong Kuang, Yuan-Chih Chuang
Format: Conference Proceeding
Language:English
Subjects:
Added delay
Adders
Computer architecture
Computer science
Design engineering
Digital signal processing
Dynamic range
Energy consumption
Portable computers
Very large scale integration
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Summary:Energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth in word size. Based on these features, this paper presents a low-power and reconfigurable signed pipelined array multiplier that can dynamically detect input range and disable the switching operations of non-effective ranges to decrease the power consumption. Moreover, the proposed pipelined multiplier can be configured to trade output precision with power consumption. Experimental results show that the proposed pipelined multiplier leads to up 40.7% power saving with a little additional area and delay overheads
DOI:10.1109/ICCCAS.2006.285132