Power Supply Noise in Delay Testing

Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis m...

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Bibliographic Details
Main Authors: Wang, Jing, H. Walker, D. M., Majhi, Ananta, Kruseman, Bram, Gronthoud, Guido, Villagra, Luis Elvira, van de Wiel, Paul, Eichenberger, Stefan
Format: Conference Proceeding
Language:English
Subjects:
Circuit faults
Circuit noise
Circuit testing
CMOS technology
Crosstalk
Delay
Noise level
Power supplies
Semiconductor device noise
Voltage
Online Access:Request full text
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Summary:Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2006.297642