At-Speed Structural Test For High-Performance ASICs

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restricti...

Full description

Saved in:
Bibliographic Details
Main Authors: Iyengar, V., Yokota, T., Yamada, K., Anemikos, T., Bassett, B., Degregorio, M., Farmer, R., Grise, G., Johnson, M., Milton, D., Taylor, M., Woytowich, F.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Circuit faults
Circuit synthesis
Circuit testing
Clocks
Delay
Design for testability
Integrated circuit testing
Logic testing
Sequential analysis
Switches
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2006.297686