A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

• Published in: IEEE transactions on electron devices 1989-10, Vol.36 (10), p.2204-2216
• Main Authors: Akinwande, A.I., Ruden, P.P., Vold, P.J., Han, C.-J., Grider, D.E., Narum, D.H., Nohava, T.E., Nohava, J.C., Arch, D.K.
• Format: Article
• Language: English
• Subjects: Analog integrated circuits; Applied sciences; Electronics; Exact sciences and technology; Fabrication; FETs; HEMTs; III-V semiconductor materials; Large scale integration; MODFET circuits; MODFET integrated circuits; Power dissipation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors; Very large scale integration
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.40901

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8*8 multiplier/accumulator, and a 4500-gate 16*16 complex multiplier have been demonstrated using enhancement-mode n/sup +/-(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1- mu m gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 mu m of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained.< >