Loading…

A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology

Saved in:

Bibliographic Details
Main Authors:	Yoon, Jae-man, Lee, Kangyoon, Park, Seung-bae, Kim, Seong-goo, Seo, Hyoung-won, Son, Young-woong, Kim, Bong-soo, Chung, Hyun-woo, Lee, Choong-ho, Lee, Won-sok, Kim, Dong-chan, Park, Donggun, Lee, Wonshik, Ryu, Byung-il
Format:	Conference Proceeding
Language:	English
Subjects:	Doping Etching Impact ionization Investments Ion implantation Leakage current Random access memory Research and development Silicon compounds Transistors
Online Access:	Request full text
Tags:	Add Tag No Tags, Be the first to tag this record!

cited_by
cites
container_end_page	260
container_issue
container_start_page	259
container_title
container_volume
creator	Yoon, Jae-man Lee, Kangyoon Park, Seung-bae Kim, Seong-goo Seo, Hyoung-won Son, Young-woong Kim, Bong-soo Chung, Hyun-woo Lee, Choong-ho Lee, Won-sok Kim, Dong-chan Park, Donggun Lee, Wonshik Ryu, Byung-il
description
doi_str_mv	10.1109/DRC.2006.305083
format	conference_proceeding
fullrecord	<record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_4097627</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4097627</ieee_id><sourcerecordid>4097627</sourcerecordid><originalsourceid>FETCH-ieee_primary_40976273</originalsourceid><addsrcrecordid>eNp9yTtPwzAUQGHzkgiQmYHljjAkXMdO7IxRSgVSQVUVda1M5aYG10Z2SpV_T4fOnOUMHyH3FHNKsX6eLNq8QKxyhiVKdkZuUEhkteB1eU6SouKYVbJkFyStj3AyyS9JQksuMyYEXpM0xi88JiSlRZmQsYEP_6stzPwBZlp9q15Duw9BuwGW8-5xqcNg1srC3FirAnRBuWji4MMTvLlB90ENxjvY-AB8WsBk0bxDq62FJgQ1wsEMW4j7T-AIbgedXm-dt74f78jVRtmo09NvycP0pWtfM6O1Xv0Es1NhXHGsRVUI9r_-AShKUOQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology</title><source>IEEE Xplore All Conference Series</source><creator>Yoon, Jae-man ; Lee, Kangyoon ; Park, Seung-bae ; Kim, Seong-goo ; Seo, Hyoung-won ; Son, Young-woong ; Kim, Bong-soo ; Chung, Hyun-woo ; Lee, Choong-ho ; Lee, Won-sok ; Kim, Dong-chan ; Park, Donggun ; Lee, Wonshik ; Ryu, Byung-il</creator><creatorcontrib>Yoon, Jae-man ; Lee, Kangyoon ; Park, Seung-bae ; Kim, Seong-goo ; Seo, Hyoung-won ; Son, Young-woong ; Kim, Bong-soo ; Chung, Hyun-woo ; Lee, Choong-ho ; Lee, Won-sok ; Kim, Dong-chan ; Park, Donggun ; Lee, Wonshik ; Ryu, Byung-il</creatorcontrib><identifier>ISSN: 1548-3770</identifier><identifier>ISBN: 9780780397484</identifier><identifier>ISBN: 0780397487</identifier><identifier>EISSN: 2640-6853</identifier><identifier>EISBN: 0780397495</identifier><identifier>EISBN: 9780780397491</identifier><identifier>DOI: 10.1109/DRC.2006.305083</identifier><language>eng</language><publisher>IEEE</publisher><subject>Doping ; Etching ; Impact ionization ; Investments ; Ion implantation ; Leakage current ; Random access memory ; Research and development ; Silicon compounds ; Transistors</subject><ispartof>2006 64th Device Research Conference, 2006, p.259-260</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4097627$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4097627$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yoon, Jae-man</creatorcontrib><creatorcontrib>Lee, Kangyoon</creatorcontrib><creatorcontrib>Park, Seung-bae</creatorcontrib><creatorcontrib>Kim, Seong-goo</creatorcontrib><creatorcontrib>Seo, Hyoung-won</creatorcontrib><creatorcontrib>Son, Young-woong</creatorcontrib><creatorcontrib>Kim, Bong-soo</creatorcontrib><creatorcontrib>Chung, Hyun-woo</creatorcontrib><creatorcontrib>Lee, Choong-ho</creatorcontrib><creatorcontrib>Lee, Won-sok</creatorcontrib><creatorcontrib>Kim, Dong-chan</creatorcontrib><creatorcontrib>Park, Donggun</creatorcontrib><creatorcontrib>Lee, Wonshik</creatorcontrib><creatorcontrib>Ryu, Byung-il</creatorcontrib><title>A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology</title><title>2006 64th Device Research Conference</title><addtitle>DRC</addtitle><subject>Doping</subject><subject>Etching</subject><subject>Impact ionization</subject><subject>Investments</subject><subject>Ion implantation</subject><subject>Leakage current</subject><subject>Random access memory</subject><subject>Research and development</subject><subject>Silicon compounds</subject><subject>Transistors</subject><issn>1548-3770</issn><issn>2640-6853</issn><isbn>9780780397484</isbn><isbn>0780397487</isbn><isbn>0780397495</isbn><isbn>9780780397491</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9yTtPwzAUQGHzkgiQmYHljjAkXMdO7IxRSgVSQVUVda1M5aYG10Z2SpV_T4fOnOUMHyH3FHNKsX6eLNq8QKxyhiVKdkZuUEhkteB1eU6SouKYVbJkFyStj3AyyS9JQksuMyYEXpM0xi88JiSlRZmQsYEP_6stzPwBZlp9q15Duw9BuwGW8-5xqcNg1srC3FirAnRBuWji4MMTvLlB90ENxjvY-AB8WsBk0bxDq62FJgQ1wsEMW4j7T-AIbgedXm-dt74f78jVRtmo09NvycP0pWtfM6O1Xv0Es1NhXHGsRVUI9r_-AShKUOQ</recordid><startdate>200606</startdate><enddate>200606</enddate><creator>Yoon, Jae-man</creator><creator>Lee, Kangyoon</creator><creator>Park, Seung-bae</creator><creator>Kim, Seong-goo</creator><creator>Seo, Hyoung-won</creator><creator>Son, Young-woong</creator><creator>Kim, Bong-soo</creator><creator>Chung, Hyun-woo</creator><creator>Lee, Choong-ho</creator><creator>Lee, Won-sok</creator><creator>Kim, Dong-chan</creator><creator>Park, Donggun</creator><creator>Lee, Wonshik</creator><creator>Ryu, Byung-il</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200606</creationdate><title>A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology</title><author>Yoon, Jae-man ; Lee, Kangyoon ; Park, Seung-bae ; Kim, Seong-goo ; Seo, Hyoung-won ; Son, Young-woong ; Kim, Bong-soo ; Chung, Hyun-woo ; Lee, Choong-ho ; Lee, Won-sok ; Kim, Dong-chan ; Park, Donggun ; Lee, Wonshik ; Ryu, Byung-il</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_40976273</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Doping</topic><topic>Etching</topic><topic>Impact ionization</topic><topic>Investments</topic><topic>Ion implantation</topic><topic>Leakage current</topic><topic>Random access memory</topic><topic>Research and development</topic><topic>Silicon compounds</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Yoon, Jae-man</creatorcontrib><creatorcontrib>Lee, Kangyoon</creatorcontrib><creatorcontrib>Park, Seung-bae</creatorcontrib><creatorcontrib>Kim, Seong-goo</creatorcontrib><creatorcontrib>Seo, Hyoung-won</creatorcontrib><creatorcontrib>Son, Young-woong</creatorcontrib><creatorcontrib>Kim, Bong-soo</creatorcontrib><creatorcontrib>Chung, Hyun-woo</creatorcontrib><creatorcontrib>Lee, Choong-ho</creatorcontrib><creatorcontrib>Lee, Won-sok</creatorcontrib><creatorcontrib>Kim, Dong-chan</creatorcontrib><creatorcontrib>Park, Donggun</creatorcontrib><creatorcontrib>Lee, Wonshik</creatorcontrib><creatorcontrib>Ryu, Byung-il</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yoon, Jae-man</au><au>Lee, Kangyoon</au><au>Park, Seung-bae</au><au>Kim, Seong-goo</au><au>Seo, Hyoung-won</au><au>Son, Young-woong</au><au>Kim, Bong-soo</au><au>Chung, Hyun-woo</au><au>Lee, Choong-ho</au><au>Lee, Won-sok</au><au>Kim, Dong-chan</au><au>Park, Donggun</au><au>Lee, Wonshik</au><au>Ryu, Byung-il</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology</atitle><btitle>2006 64th Device Research Conference</btitle><stitle>DRC</stitle><date>2006-06</date><risdate>2006</risdate><spage>259</spage><epage>260</epage><pages>259-260</pages><issn>1548-3770</issn><eissn>2640-6853</eissn><isbn>9780780397484</isbn><isbn>0780397487</isbn><eisbn>0780397495</eisbn><eisbn>9780780397491</eisbn><pub>IEEE</pub><doi>10.1109/DRC.2006.305083</doi></addata></record>
fulltext	fulltext_linktorsrc
identifier	ISSN: 1548-3770
ispartof	2006 64th Device Research Conference, 2006, p.259-260
issn	1548-3770 2640-6853
language	eng
recordid	cdi_ieee_primary_4097627
source	IEEE Xplore All Conference Series
subjects	Doping Etching Impact ionization Investments Ion implantation Leakage current Random access memory Research and development Silicon compounds Transistors
title	A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology
url	http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T14%3A58%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Novel%20Low%20Leakage%20Current%20VPT(Vertical%20Pillar%20Transistor)%20Integration%20for%204F2%20DRAM%20Cell%20Array%20with%20sub%2040%20nm%20Technology&rft.btitle=2006%2064th%20Device%20Research%20Conference&rft.au=Yoon,%20Jae-man&rft.date=2006-06&rft.spage=259&rft.epage=260&rft.pages=259-260&rft.issn=1548-3770&rft.eissn=2640-6853&rft.isbn=9780780397484&rft.isbn_list=0780397487&rft_id=info:doi/10.1109/DRC.2006.305083&rft.eisbn=0780397495&rft.eisbn_list=9780780397491&rft_dat=%3Cieee_CHZPO%3E4097627%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-ieee_primary_40976273%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4097627&rfr_iscdi=true