An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms

This paper describes an architecture dedicated to the realtime processing of census correlation in the context of the realization of passive stereovision sensors. Although DSP circuits have dramatically increased their performances in terms of frequency (about 600 MHz today), DSP cores (several Mult...

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Bibliographic Details
Main Authors: Naoulou, A., Boizard, J.-L., Fourniols, J.Y., Devy, M.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Circuits
Computer architecture
Computer vision
Digital signal processing
Field programmable gate arrays
Frequency
Parallel architectures
Pipelines
Sensor phenomena and characterization
Online Access:Request full text
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Summary:This paper describes an architecture dedicated to the realtime processing of census correlation in the context of the realization of passive stereovision sensors. Although DSP circuits have dramatically increased their performances in terms of frequency (about 600 MHz today), DSP cores (several Multipliers Accumulators) and pipelines (Super Harvard Architectures for example), FPGA circuits remain the best way to design massive parallel architectures when ultra fast algorithms computation are needed like it is the case in real time vision systems for collision avoidance.
ISSN:1946-147X
1946-1488
DOI:10.1109/FPL.2006.311322