An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures

This paper introduces an application mapping methodology and case study for multiprocessor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is profiled, parallelized when possible, and then its components are moved...

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Bibliographic Details
Main Authors: Beltrame, G., Sciuto, D., Silvano, C., Paulin, P., Bensoudane, E.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Code standards
Computer architecture
Energy consumption
Hardware
Microarchitecture
Power system modeling
Programming profession
Space exploration
Timing
Online Access:Request full text
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Summary:This paper introduces an application mapping methodology and case study for multiprocessor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is profiled, parallelized when possible, and then its components are moved to hardware implementation when necessary to satisfy performance and power constraints. The key contribution of this work is a methodology for high-level hardware/software partitioning that allows the designer to use the same code for both hardware and software models for simulation, providing nevertheless preliminary estimations for timing and power consumption. The methodology has been applied to the co-exploration of an industrial case study: an MPEG4 VGA realtime encoder
ISSN:2324-8432
DOI:10.1109/VLSISOC.2006.313219