Formal Verifications in Modern Chip Designs

Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, desi...

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Bibliographic Details
Main Author: Kei-Yong Khoo
Format: Conference Proceeding
Language:English
Subjects:
Chip scale packaging
Conferences
Formal verification
Logic design
Power system management
System testing
Technology management
Online Access:Request full text
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Description
Summary:Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, design-constraint management, and low-power design verifications. In addition, we examine modern and emerging design styles and techniques, and requirements on formal technologies to meet the new verification challenges
ISSN:1552-6674
2471-7827
DOI:10.1109/HLDVT.2006.320001